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gpu-compute, hsail: pass GPUDynInstPtr to getRegisterIndex()

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for HSAIL an operand's indices into the register files may be calculated
trivially, because the operands are always read from a register file, or are
an immediate.

for machine ISA, however, an op selector may specify special registers, or
may specify special SGPRs with an alias op selector value. the location of
some of the special registers values are dependent on the size of the RF
in some cases. here we add a way for the underlying getRegisterIndex()
method to know about the size of the RFs, so that it may find the relative
positions of the special register values.
This commit is contained in:
Tony Gutierrez 2016-10-26 22:47:49 -04:00
parent aa7364276f
commit b63eb1302b
9 changed files with 85 additions and 31 deletions
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12
src/arch/hsail/insts/branch.hh
View file

@ -95,7 +95,9 @@ namespace HsailISA
return target.opSize();
}
int getRegisterIndex(int operandIndex) override {
int
getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
{
assert(operandIndex >= 0 && operandIndex < getNumOperands());
return target.regIndex();
}
@ -223,7 +225,9 @@ namespace HsailISA
else
return 1;
}
int getRegisterIndex(int operandIndex) override {
int
getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
{
assert(operandIndex >= 0 && operandIndex < getNumOperands());
if (!operandIndex)
return target.regIndex();
@ -370,7 +374,9 @@ namespace HsailISA
assert(operandIndex >= 0 && operandIndex < getNumOperands());
return target.opSize();
}
int getRegisterIndex(int operandIndex) override {
int
getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
{
assert(operandIndex >= 0 && operandIndex < getNumOperands());
return target.regIndex();
}

44
src/arch/hsail/insts/decl.hh
View file

@ -178,7 +178,9 @@ namespace HsailISA
else
return dest.opSize();
}
int getRegisterIndex(int operandIndex) {
int
getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst)
{
assert(operandIndex >= 0 && operandIndex < getNumOperands());
if (operandIndex < NumSrcOperands)
@ -313,7 +315,10 @@ namespace HsailISA
else
return dest.opSize();
}
int getRegisterIndex(int operandIndex) {
int
getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst)
{
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
if (!operandIndex)
return src0.regIndex();
@ -477,7 +482,10 @@ namespace HsailISA
else
return dest.opSize();
}
int getRegisterIndex(int operandIndex) {
int
getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst)
{
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
if (!operandIndex)
return src0.regIndex();
@ -643,7 +651,7 @@ namespace HsailISA
return -1;
//handle positive and negative numbers
T tmp = (src0 < 0) ? (~src0) : (src0);
T tmp = ((int64_t)src0 < 0) ? (~src0) : (src0);
//the starting pos is MSB
int pos = 8 * sizeof(T) - 1;
@ -732,7 +740,12 @@ namespace HsailISA
bool isSrcOperand(int operandIndex) { return false; }
bool isDstOperand(int operandIndex) { return false; }
int getOperandSize(int operandIndex) { return 0; }
int getRegisterIndex(int operandIndex) { return -1; }
int
getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst)
{
return -1;
}
int numSrcRegOperands() { return 0; }
int numDstRegOperands() { return 0; }
@ -777,10 +790,14 @@ namespace HsailISA
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return dest.opSize();
}
int getRegisterIndex(int operandIndex) {
int
getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst)
{
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return dest.regIndex();
}
int numSrcRegOperands() { return 0; }
int numDstRegOperands() { return dest.isVectorRegister(); }
int getNumOperands() { return 1; }
@ -848,10 +865,14 @@ namespace HsailISA
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return dest.opSize();
}
int getRegisterIndex(int operandIndex) {
int
getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst)
{
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return dest.regIndex();
}
int numSrcRegOperands() { return 0; }
int numDstRegOperands() { return dest.isVectorRegister(); }
int getNumOperands() { return 1; }
@ -1171,8 +1192,13 @@ namespace HsailISA
bool isScalarRegister(int operandIndex) { return false; }
bool isSrcOperand(int operandIndex) { return false; }
bool isDstOperand(int operandIndex) { return false; }
int getOperandSize(int operandIndex) { return 0; }
int getRegisterIndex(int operandIndex) { return -1; }
int getOperandSize(int operandIndex) { return 0; }
int
getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst)
{
return -1;
}
void
execute(GPUDynInstPtr gpuDynInst)

18
src/arch/hsail/insts/mem.hh
View file

@ -146,7 +146,8 @@ namespace HsailISA
return((operandIndex == 0) ? dest.opSize() :
this->addr.opSize());
}
int getRegisterIndex(int operandIndex) override
int
getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
{
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return((operandIndex == 0) ? dest.regIndex() :
@ -377,7 +378,8 @@ namespace HsailISA
return((operandIndex == 0) ? dest.opSize() :
this->addr.opSize());
}
int getRegisterIndex(int operandIndex) override
int
getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
{
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
return((operandIndex == 0) ? dest.regIndex() :
@ -670,7 +672,8 @@ namespace HsailISA
AddrOperandType>::dest.opSize());
return 0;
}
int getRegisterIndex(int operandIndex) override
int
getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
{
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
if ((num_dest_operands != getNumOperands()) &&
@ -934,7 +937,8 @@ namespace HsailISA
assert(operandIndex >= 0 && operandIndex < getNumOperands());
return !operandIndex ? src.opSize() : this->addr.opSize();
}
int getRegisterIndex(int operandIndex) override
int
getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
{
assert(operandIndex >= 0 && operandIndex < getNumOperands());
return !operandIndex ? src.regIndex() : this->addr.regIndex();
@ -1144,7 +1148,8 @@ namespace HsailISA
AddrOperandType>::src.opSize();
return 0;
}
int getRegisterIndex(int operandIndex) override
int
getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
{
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
if (operandIndex == num_src_operands)
@ -1433,7 +1438,8 @@ namespace HsailISA
else
return(dest.opSize());
}
int getRegisterIndex(int operandIndex)
int
getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst)
{
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
if (operandIndex < NumSrcOperands)

6
src/gpu-compute/condition_register_state.cc
View file

@ -62,19 +62,19 @@ ConditionRegisterState::init(uint32_t _size)
}
void
ConditionRegisterState::exec(GPUStaticInst *ii, Wavefront *w)
ConditionRegisterState::exec(GPUDynInstPtr ii, Wavefront *w)
{
// iterate over all operands
for (auto i = 0; i < ii->getNumOperands(); ++i) {
// is this a condition register destination operand?
if (ii->isCondRegister(i) && ii->isDstOperand(i)) {
// mark the register as busy
markReg(ii->getRegisterIndex(i), 1);
markReg(ii->getRegisterIndex(i, ii), 1);
uint32_t pipeLen = w->computeUnit->spBypassLength();
// schedule an event for marking the register as ready
w->computeUnit->
registerEvent(w->simdId, ii->getRegisterIndex(i),
registerEvent(w->simdId, ii->getRegisterIndex(i, ii),
ii->getOperandSize(i),
w->computeUnit->shader->tick_cnt +
w->computeUnit->shader->ticks(pipeLen), 0);

2
src/gpu-compute/condition_register_state.hh
View file

@ -87,7 +87,7 @@ class ConditionRegisterState
}
int numRegs() { return c_reg.size(); }
void exec(GPUStaticInst *ii, Wavefront *w);
void exec(GPUDynInstPtr ii, Wavefront *w);
private:
ComputeUnit* computeUnit;

12
src/gpu-compute/gpu_dyn_inst.cc
View file

@ -102,10 +102,16 @@ GPUDynInst::isScalarRegister(int operandIdx)
return _staticInst->isScalarRegister(operandIdx);
}
int
GPUDynInst::getRegisterIndex(int operandIdx)
bool
GPUDynInst::isCondRegister(int operandIdx)
{
return _staticInst->getRegisterIndex(operandIdx);
return _staticInst->isCondRegister(operandIdx);
}
int
GPUDynInst::getRegisterIndex(int operandIdx, GPUDynInstPtr gpuDynInst)
{
return _staticInst->getRegisterIndex(operandIdx, gpuDynInst);
}
int

3
src/gpu-compute/gpu_dyn_inst.hh
View file

@ -194,7 +194,8 @@ class GPUDynInst : public GPUExecContext
int getNumOperands();
bool isVectorRegister(int operandIdx);
bool isScalarRegister(int operandIdx);
int getRegisterIndex(int operandIdx);
bool isCondRegister(int operandIdx);
int getRegisterIndex(int operandIdx, GPUDynInstPtr gpuDynInst);
int getOperandSize(int operandIdx);
bool isDstOperand(int operandIdx);
bool isSrcOperand(int operandIdx);

13
src/gpu-compute/gpu_static_inst.hh
View file

@ -83,7 +83,10 @@ class GPUStaticInst : public GPUStaticInstFlags
virtual bool isSrcOperand(int operandIndex) = 0;
virtual bool isDstOperand(int operandIndex) = 0;
virtual int getOperandSize(int operandIndex) = 0;
virtual int getRegisterIndex(int operandIndex) = 0;
virtual int getRegisterIndex(int operandIndex,
GPUDynInstPtr gpuDynInst) = 0;
virtual int numDstRegOperands() = 0;
virtual int numSrcRegOperands() = 0;
@ -286,7 +289,13 @@ class KernelLaunchStaticInst : public GPUStaticInst
bool isSrcOperand(int operandIndex) { return false; }
bool isDstOperand(int operandIndex) { return false; }
int getOperandSize(int operandIndex) { return 0; }
int getRegisterIndex(int operandIndex) { return 0; }
int
getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
{
return 0;
}
int numDstRegOperands() { return 0; }
int numSrcRegOperands() { return 0; }
bool isValid() const { return true; }

6
src/gpu-compute/vector_register_file.cc
View file

@ -121,7 +121,7 @@ VectorRegisterFile::operandsReady(Wavefront *w, GPUDynInstPtr ii) const
{
for (int i = 0; i < ii->getNumOperands(); ++i) {
if (ii->isVectorRegister(i)) {
uint32_t vgprIdx = ii->getRegisterIndex(i);
uint32_t vgprIdx = ii->getRegisterIndex(i, ii);
uint32_t pVgpr = w->remap(vgprIdx, ii->getOperandSize(i), 1);
if (regBusy(pVgpr, ii->getOperandSize(i)) == 1) {
@ -160,7 +160,7 @@ VectorRegisterFile::exec(GPUDynInstPtr ii, Wavefront *w)
// iterate over all register destination operands
for (int i = 0; i < ii->getNumOperands(); ++i) {
if (ii->isVectorRegister(i) && ii->isDstOperand(i)) {
uint32_t physReg = w->remap(ii->getRegisterIndex(i),
uint32_t physReg = w->remap(ii->getRegisterIndex(i, ii),
ii->getOperandSize(i), 1);
// mark the destination vector register as busy
@ -216,7 +216,7 @@ VectorRegisterFile::updateResources(Wavefront *w, GPUDynInstPtr ii)
// iterate over all register destination operands
for (int i = 0; i < ii->getNumOperands(); ++i) {
if (ii->isVectorRegister(i) && ii->isDstOperand(i)) {
uint32_t physReg = w->remap(ii->getRegisterIndex(i),
uint32_t physReg = w->remap(ii->getRegisterIndex(i, ii),
ii->getOperandSize(i), 1);
// set the in-flight status of the destination vector register
preMarkReg(physReg, ii->getOperandSize(i), 1);