sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
gem5/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
Steve Reinhardt fbc1feb39a tests: update reference outputs 
Apparently only stats.txt was updated the last time, so
this changeset updates other reference output files
(config.ini, simout, simerr, ruby.stats) so that
test output diffs should not be cluttered with irrelevant
changes.  There are a few stats.txt updates too, but
they are in the minority.
2013-09-28 15:25:17 -04:00

524 lines
10 KiB
INI
Raw Blame History

[root]
type=Root
children=system
full_system=true
time_sync_enable=false
time_sync_period=200000000
time_sync_spin_threshold=200000
[system]
type=SparcSystem
children=bridge clk_domain cpu cpu_clk_domain disk0 hypervisor_desc intrctrl iobus membus nvram partition_desc physmem0 physmem1 rom t1000 voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
hypervisor_addr=1099243257856
hypervisor_bin=/dist/m5/system/binaries/q_new.bin
hypervisor_desc=system.hypervisor_desc
hypervisor_desc_addr=133446500352
hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
mem_ranges=1048576:68157439 2147483648:2415919103
memories=system.rom system.physmem1 system.hypervisor_desc system.physmem0 system.nvram system.partition_desc
num_work_ids=16
nvram=system.nvram
nvram_addr=133429198848
nvram_bin=/dist/m5/system/binaries/nvram1
openboot_addr=1099243716608
openboot_bin=/dist/m5/system/binaries/openboot_new.bin
partition_desc=system.partition_desc
partition_desc_addr=133445976064
partition_desc_bin=/dist/m5/system/binaries/1up-md.bin
readfile=tests/halt.sh
reset_addr=1099243192320
reset_bin=/dist/m5/system/binaries/reset_new.bin
rom=system.rom
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.bridge]
type=Bridge
clk_domain=system.clk_domain
delay=100
ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463
req_size=16
resp_size=16
master=system.iobus.slave[0]
slave=system.membus.master[2]
[system.clk_domain]
type=SrcClockDomain
clock=2
voltage_domain=system.voltage_domain
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts isa itb tracer
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
simpoint_interval=100000000
simpoint_profile=false
simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
switched_out=false
system=system
tracer=system.cpu.tracer
width=1
workload=
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=SparcTLB
size=64
[system.cpu.interrupts]
type=SparcInterrupts
[system.cpu.isa]
type=SparcISA
[system.cpu.itb]
type=SparcTLB
size=64
[system.cpu.tracer]
type=ExeTracer
[system.cpu_clk_domain]
type=SrcClockDomain
clock=2
voltage_domain=system.voltage_domain
[system.disk0]
type=MmDisk
children=image
clk_domain=system.clk_domain
image=system.disk0.image
pio_addr=134217728000
pio_latency=200
system=system
pio=system.iobus.master[14]
[system.disk0.image]
type=CowDiskImage
children=child
child=system.disk0.image.child
image_file=
read_only=false
table_size=65536
[system.disk0.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/disk.s10hw2
read_only=true
[system.hypervisor_desc]
type=SimpleMemory
bandwidth=0.000000
clk_domain=system.clk_domain
conf_table_reported=true
in_addr_map=true
latency=60
latency_var=0
null=false
range=133446500352:133446508543
port=system.membus.master[5]
[system.intrctrl]
type=IntrControl
sys=system
[system.iobus]
type=NoncoherentBus
clk_domain=system.clk_domain
header_cycles=1
use_default_range=false
width=8
master=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.disk0.pio
slave=system.bridge.master
[system.membus]
type=CoherentBus
children=badaddr_responder
clk_domain=system.clk_domain
header_cycles=1
system=system
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
master=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.rom.port system.nvram.port system.hypervisor_desc.port system.partition_desc.port system.physmem0.port system.physmem1.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.membus.badaddr_responder]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=0
pio_latency=200
pio_size=8
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.membus.default
[system.nvram]
type=SimpleMemory
bandwidth=0.000000
clk_domain=system.clk_domain
conf_table_reported=true
in_addr_map=true
latency=60
latency_var=0
null=false
range=133429198848:133429207039
port=system.membus.master[4]
[system.partition_desc]
type=SimpleMemory
bandwidth=0.000000
clk_domain=system.clk_domain
conf_table_reported=true
in_addr_map=true
latency=60
latency_var=0
null=false
range=133445976064:133445984255
port=system.membus.master[6]
[system.physmem0]
type=SimpleMemory
bandwidth=0.000000
clk_domain=system.clk_domain
conf_table_reported=true
in_addr_map=true
latency=60
latency_var=0
null=false
range=1048576:68157439
port=system.membus.master[7]
[system.physmem1]
type=SimpleMemory
bandwidth=0.000000
clk_domain=system.clk_domain
conf_table_reported=true
in_addr_map=true
latency=60
latency_var=0
null=false
range=2147483648:2415919103
port=system.membus.master[8]
[system.rom]
type=SimpleMemory
bandwidth=0.000000
clk_domain=system.clk_domain
conf_table_reported=true
in_addr_map=true
latency=60
latency_var=0
null=false
range=1099243192320:1099251580927
port=system.membus.master[3]
[system.t1000]
type=T1000
children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hterm htod hvuart iob pterm puart0
intrctrl=system.intrctrl
system=system
[system.t1000.fake_clk]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=644245094400
pio_latency=200
pio_size=4294967296
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[0]
[system.t1000.fake_jbi]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=549755813888
pio_latency=200
pio_size=4294967296
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[11]
[system.t1000.fake_l2_1]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=725849473024
pio_latency=200
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=1
ret_data8=255
system=system
update_data=true
warn_access=
pio=system.iobus.master[2]
[system.t1000.fake_l2_2]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=725849473088
pio_latency=200
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=1
ret_data8=255
system=system
update_data=true
warn_access=
pio=system.iobus.master[3]
[system.t1000.fake_l2_3]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=725849473152
pio_latency=200
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=1
ret_data8=255
system=system
update_data=true
warn_access=
pio=system.iobus.master[4]
[system.t1000.fake_l2_4]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=725849473216
pio_latency=200
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=1
ret_data8=255
system=system
update_data=true
warn_access=
pio=system.iobus.master[5]
[system.t1000.fake_l2esr_1]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=734439407616
pio_latency=200
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=0
ret_data8=255
system=system
update_data=true
warn_access=
pio=system.iobus.master[6]
[system.t1000.fake_l2esr_2]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=734439407680
pio_latency=200
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=0
ret_data8=255
system=system
update_data=true
warn_access=
pio=system.iobus.master[7]
[system.t1000.fake_l2esr_3]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=734439407744
pio_latency=200
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=0
ret_data8=255
system=system
update_data=true
warn_access=
pio=system.iobus.master[8]
[system.t1000.fake_l2esr_4]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=734439407808
pio_latency=200
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=0
ret_data8=255
system=system
update_data=true
warn_access=
pio=system.iobus.master[9]
[system.t1000.fake_membnks]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=648540061696
pio_latency=200
pio_size=16384
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=0
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[1]
[system.t1000.fake_ssi]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=1095216660480
pio_latency=200
pio_size=268435456
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[10]
[system.t1000.hterm]
type=Terminal
intr_control=system.intrctrl
number=0
output=true
port=3456
[system.t1000.htod]
type=DumbTOD
clk_domain=system.clk_domain
pio_addr=1099255906296
pio_latency=200
system=system
time=Thu Jan 1 00:00:00 2009
pio=system.membus.master[1]
[system.t1000.hvuart]
type=Uart8250
clk_domain=system.clk_domain
pio_addr=1099255955456
pio_latency=200
platform=system.t1000
system=system
terminal=system.t1000.hterm
pio=system.iobus.master[13]
[system.t1000.iob]
type=Iob
clk_domain=system.clk_domain
pio_latency=2
platform=system.t1000
system=system
pio=system.membus.master[0]
[system.t1000.pterm]
type=Terminal
intr_control=system.intrctrl
number=0
output=true
port=3456
[system.t1000.puart0]
type=Uart8250
clk_domain=system.clk_domain
pio_addr=133412421632
pio_latency=200
platform=system.t1000
system=system
terminal=system.t1000.pterm
pio=system.iobus.master[12]
[system.voltage_domain]
type=VoltageDomain
voltage=1.000000
Reference in a new issue View git blame Copy permalink