445 lines
47 KiB
Plaintext
445 lines
47 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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global.BPredUnit.BTBHits 649 # Number of BTB hits
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global.BPredUnit.BTBLookups 1748 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 1246 # Number of conditional branches predicted
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global.BPredUnit.lookups 2108 # Number of BP lookups
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global.BPredUnit.usedRAS 301 # Number of times the RAS was used to get a target.
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host_inst_rate 87257 # Simulator instruction rate (inst/s)
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host_mem_usage 198272 # Number of bytes of host memory used
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host_seconds 0.07 # Real time elapsed on the host
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host_tick_rate 171219532 # Simulator tick rate (ticks/s)
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memdepunit.memDep.conflictingLoads 36 # Number of conflicting loads.
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memdepunit.memDep.conflictingStores 28 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 2214 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 1262 # Number of stores inserted to the mem dependence unit.
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 6297 # Number of instructions simulated
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sim_seconds 0.000012 # Number of seconds simulated
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sim_ticks 12391500 # Number of ticks simulated
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system.cpu.commit.COM:branches 1012 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 120 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle.samples 12114
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system.cpu.commit.COM:committed_per_cycle.min_value 0
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0 9249 7634.97%
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1 1607 1326.56%
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2 479 395.41%
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3 271 223.71%
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4 137 113.09%
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5 121 99.88%
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6 87 71.82%
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7 43 35.50%
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8 120 99.06%
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system.cpu.commit.COM:committed_per_cycle.max_value 8
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system.cpu.commit.COM:committed_per_cycle.end_dist
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system.cpu.commit.COM:count 6314 # Number of instructions committed
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system.cpu.commit.COM:loads 1168 # Number of loads committed
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs 2030 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 350 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 6314 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 4365 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 6297 # Number of Instructions Simulated
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system.cpu.committedInsts_total 6297 # Number of Instructions Simulated
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system.cpu.cpi 3.935842 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 3.935842 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 1738 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 34857.142857 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36237.373737 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 1577 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 5612000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.092635 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 161 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 62 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 3587500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.056962 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 99 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 862 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 35059.055118 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35660.919540 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 481 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 13357500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.441995 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 381 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 294 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 3102500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.100928 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 12.156977 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 2600 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 34999.077491 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 35967.741935 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 2058 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 18969500 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.208462 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 542 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 356 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 6690000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.071538 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 186 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 2600 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 34999.077491 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 35967.741935 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 2058 # number of overall hits
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system.cpu.dcache.overall_miss_latency 18969500 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.208462 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 542 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 356 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 6690000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.071538 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 186 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.sampled_refs 172 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 109.051613 # Cycle average of tags in use
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system.cpu.dcache.total_refs 2091 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 0 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 1043 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 71 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 168 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 11945 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 8815 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 2203 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 855 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 208 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 54 # Number of cycles decode is unblocking
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system.cpu.dtb.accesses 2892 # DTB accesses
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system.cpu.dtb.acv 0 # DTB access violations
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system.cpu.dtb.hits 2831 # DTB hits
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system.cpu.dtb.misses 61 # DTB misses
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system.cpu.dtb.read_accesses 1821 # DTB read accesses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_hits 1785 # DTB read hits
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system.cpu.dtb.read_misses 36 # DTB read misses
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system.cpu.dtb.write_accesses 1071 # DTB write accesses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_hits 1046 # DTB write hits
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system.cpu.dtb.write_misses 25 # DTB write misses
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system.cpu.fetch.Branches 2108 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 1704 # Number of cache lines fetched
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system.cpu.fetch.Cycles 4044 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 264 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 12761 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 482 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.085055 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 1704 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 950 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 0.514889 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist.samples 12970
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system.cpu.fetch.rateDist.min_value 0
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0 10663 8221.28%
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1 241 185.81%
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2 214 165.00%
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3 169 130.30%
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4 208 160.37%
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5 163 125.67%
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6 215 165.77%
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7 128 98.69%
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8 969 747.11%
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system.cpu.fetch.rateDist.max_value 8
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system.cpu.fetch.rateDist.end_dist
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system.cpu.icache.ReadReq_accesses 1704 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 35319.248826 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 35254.870130 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 1278 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 15046000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.250000 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 426 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 118 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 10858500 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.180751 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 308 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 4.149351 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 1704 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 35319.248826 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 35254.870130 # average overall mshr miss latency
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system.cpu.icache.demand_hits 1278 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 15046000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.250000 # miss rate for demand accesses
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system.cpu.icache.demand_misses 426 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 118 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 10858500 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.180751 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 308 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 1704 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 35319.248826 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 35254.870130 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 1278 # number of overall hits
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system.cpu.icache.overall_miss_latency 15046000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.250000 # miss rate for overall accesses
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system.cpu.icache.overall_misses 426 # number of overall misses
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system.cpu.icache.overall_mshr_hits 118 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 10858500 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.180751 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 308 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.icache.replacements 0 # number of replacements
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system.cpu.icache.sampled_refs 308 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 160.409405 # Cycle average of tags in use
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system.cpu.icache.total_refs 1278 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idleCycles 11814 # Total number of cycles that the CPU has spent unscheduled due to idling
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system.cpu.iew.EXEC:branches 1375 # Number of branches executed
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system.cpu.iew.EXEC:nop 76 # number of nop insts executed
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system.cpu.iew.EXEC:rate 0.355148 # Inst execution rate
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system.cpu.iew.EXEC:refs 2900 # number of memory reference insts executed
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system.cpu.iew.EXEC:stores 1073 # Number of stores executed
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system.cpu.iew.EXEC:swp 0 # number of swp insts executed
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system.cpu.iew.WB:consumers 5878 # num instructions consuming a value
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system.cpu.iew.WB:count 8512 # cumulative count of insts written-back
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system.cpu.iew.WB:fanout 0.747873 # average fanout of values written-back
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system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
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system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.iew.WB:producers 4396 # num instructions producing a value
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system.cpu.iew.WB:rate 0.343447 # insts written-back per cycle
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system.cpu.iew.WB:sent 8611 # cumulative count of insts sent to commit
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system.cpu.iew.branchMispredicts 406 # Number of branch mispredicts detected at execute
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system.cpu.iew.iewBlockCycles 66 # Number of cycles IEW is blocking
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system.cpu.iew.iewDispLoadInsts 2214 # Number of dispatched load instructions
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system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions
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system.cpu.iew.iewDispSquashedInsts 181 # Number of squashed instructions skipped by dispatch
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system.cpu.iew.iewDispStoreInsts 1262 # Number of dispatched store instructions
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system.cpu.iew.iewDispatchedInsts 10713 # Number of instructions dispatched to IQ
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system.cpu.iew.iewExecLoadInsts 1827 # Number of load instructions executed
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system.cpu.iew.iewExecSquashedInsts 299 # Number of squashed instructions skipped in execute
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system.cpu.iew.iewExecutedInsts 8802 # Number of executed instructions
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system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
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system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
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system.cpu.iew.iewSquashCycles 855 # Number of cycles IEW is squashing
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system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking
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system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
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system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
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system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores
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system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
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system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
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system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 64 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 1046 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread.0.squashedStores 400 # Number of stores squashed
|
|
system.cpu.iew.memOrderViolationEvents 64 # Number of memory order violations
|
|
system.cpu.iew.predictedNotTakenIncorrect 290 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.predictedTakenIncorrect 116 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.ipc 0.254075 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.254075 # IPC: Total IPC of All Threads
|
|
system.cpu.iq.ISSUE:FU_type_0 9101 # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|
No_OpClass 2 0.02% # Type of FU issued
|
|
IntAlu 6072 66.72% # Type of FU issued
|
|
IntMult 1 0.01% # Type of FU issued
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
FloatAdd 2 0.02% # Type of FU issued
|
|
FloatCmp 0 0.00% # Type of FU issued
|
|
FloatCvt 0 0.00% # Type of FU issued
|
|
FloatMult 0 0.00% # Type of FU issued
|
|
FloatDiv 0 0.00% # Type of FU issued
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
|
MemRead 1928 21.18% # Type of FU issued
|
|
MemWrite 1096 12.04% # Type of FU issued
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 93 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.010219 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
No_OpClass 0 0.00% # attempts to use FU when none available
|
|
IntAlu 2 2.15% # attempts to use FU when none available
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
FloatAdd 0 0.00% # attempts to use FU when none available
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
|
MemRead 56 60.22% # attempts to use FU when none available
|
|
MemWrite 35 37.63% # attempts to use FU when none available
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 12970
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
|
0 8890 6854.28%
|
|
1 1667 1285.27%
|
|
2 1037 799.54%
|
|
3 696 536.62%
|
|
4 340 262.14%
|
|
5 189 145.72%
|
|
6 103 79.41%
|
|
7 35 26.99%
|
|
8 13 10.02%
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
system.cpu.iq.ISSUE:rate 0.367213 # Inst issue rate
|
|
system.cpu.iq.iqInstsAdded 10614 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 9101 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 3909 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 43 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 2399 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.itb.accesses 1737 # ITB accesses
|
|
system.cpu.itb.acv 0 # ITB acv
|
|
system.cpu.itb.hits 1704 # ITB hits
|
|
system.cpu.itb.misses 33 # ITB misses
|
|
system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34404.109589 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31294.520548 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_miss_latency 2511500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2284500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_accesses 407 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34399.014778 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31224.137931 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_miss_latency 13966000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.997543 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_misses 406 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 12677000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997543 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_misses 406 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34250 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 479500 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_refs 0.002551 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.demand_accesses 480 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_avg_miss_latency 34399.791232 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31234.864301 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_miss_latency 16477500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_rate 0.997917 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_misses 479 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_miss_latency 14961500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.997917 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_misses 479 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.overall_accesses 480 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_avg_miss_latency 34399.791232 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31234.864301 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_hits 1 # number of overall hits
|
|
system.cpu.l2cache.overall_miss_latency 16477500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_rate 0.997917 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses 479 # number of overall misses
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_miss_latency 14961500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.997917 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_misses 479 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.sampled_refs 392 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.tagsinuse 215.607487 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
system.cpu.numCycles 24784 # number of cpu cycles simulated
|
|
system.cpu.rename.RENAME:BlockCycles 319 # Number of cycles rename is blocking
|
|
system.cpu.rename.RENAME:CommittedMaps 4537 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:IQFullEvents 8 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.RENAME:IdleCycles 8963 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 264 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:RenameLookups 14577 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 11538 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 8602 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 2108 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 855 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:UnblockCycles 294 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 4065 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:serializeStallCycles 431 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 719 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed
|
|
system.cpu.timesIdled 242 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|