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Andreas Sandberg d2254e034e dev, arm: Fix multi-core KVM race in the generic timer The generic timer sometimes needs to access global state. This can lead to race conditions when simulating a multi-core KVM system where each core lives in its own thread. In that case, the setMiscReg and readMiscReg methods are called from the thread owning the CPU and not the global device thread. Change-Id: Ie3e982258648c8562cce0b30a0c122dfbfaf42cd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2460 Reviewed-by: Weiping Liao <weipingliao@google.com>		2017-04-03 16:37:55 +00:00
build_opts	riscv: [Patch 5/5] Added missing support for timing CPU models	2016-11-30 17:10:28 -05:00
configs	config: exit with fatal() if error	2017-03-01 14:21:56 +00:00
ext	scons: Automatically add a git commit message hook	2017-03-01 11:42:39 +00:00
src	dev, arm: Fix multi-core KVM race in the generic timer	2017-04-03 16:37:55 +00:00
system	arm, config: Add an example ARM big.LITTLE(tm) configuration script	2016-07-21 17:19:16 +01:00
tests	tests: Warn not fail when reading invalid pickle status files	2017-03-16 13:51:37 +00:00
util	util: Add a tool to list outgoing/incoming changes	2017-03-21 10:26:57 +00:00
.gitignore	misc: Add dtb files to the ignore list for git and mercurial	2017-02-21 14:14:44 +00:00
.hgignore	misc: Add dtb files to the ignore list for git and mercurial	2017-02-21 14:14:44 +00:00
.hgtags	Added tag stable_2015_09_03 for changeset 60eb3fef9c2d	2015-09-03 15:38:46 -05:00
CONTRIBUTING.md	misc: add copyright/name information for contribution	2017-03-20 14:31:32 +00:00
COPYING	ruby: fix and/or precedence in slicc	2017-03-01 11:58:37 +00:00
LICENSE	copyright: Add code for finding all copyright blocks and create a COPYING file	2011-06-02 17:36:07 -07:00
README	misc: README direct to website for dependencies	2014-08-26 10:12:04 -04:00
SConstruct	scons: Collapse symlinks when installing git hooks.	2017-03-26 17:40:57 +00:00

README

This is the gem5 simulator.

The main website can be found at http://www.gem5.org

A good starting point is http://www.gem5.org/Introduction, and for
more information about building the simulator and getting started
please see http://www.gem5.org/Documentation and
http://www.gem5.org/Tutorials.

To build gem5, you will need the following software: g++ or clang,
Python (gem5 links in the Python interpreter), SCons, SWIG, zlib, m4,
and lastly protobuf if you want trace capture and playback
support. Please see http://www.gem5.org/Dependencies for more details
concerning the minimum versions of the aforementioned tools.

Once you have all dependencies resolved, type 'scons
build/<ARCH>/gem5.opt' where ARCH is one of ALPHA, ARM, NULL, MIPS,
POWER, SPARC, or X86. This will build an optimized version of the gem5
binary (gem5.opt) for the the specified architecture. See
http://www.gem5.org/Build_System for more details and options.

With the simulator built, have a look at
http://www.gem5.org/Running_gem5 for more information on how to use
gem5.

The basic source release includes these subdirectories:
   - configs: example simulation configuration scripts
   - ext: less-common external packages needed to build gem5
   - src: source code of the gem5 simulator
   - system: source for some optional system software for simulated systems
   - tests: regression tests
   - util: useful utility programs and files

To run full-system simulations, you will need compiled system firmware
(console and PALcode for Alpha), kernel binaries and one or more disk
images. Please see the gem5 download page for these items at
http://www.gem5.org/Download

If you have questions, please send mail to gem5-users@gem5.org

Enjoy using gem5 and please share your modifications and extensions.