5b1804e3bd
A cluster over here means a set of controllers that can be accessed only by a certain set of cores. For example, consider a two level hierarchy. Assume there are 4 L1 controllers (private) and 2 L2 controllers. We can have two different hierarchies here: a. the address space is partitioned between the two L2 controllers. Each L1 controller accesses both the L2 controllers. In this case, each L1 controller is a cluster initself. b. both the L2 controllers can cache any address. An L1 controller has access to only one of the L2 controllers. In this case, each L2 controller along with the L1 controllers that access it, form a cluster. This patch allows for each controller to have a cluster ID, which is 0 by default. By setting the cluster ID properly, one can instantiate hierarchies with clusters. Note that the coherence protocol might have to be changed as well.
101 lines
3.5 KiB
C++
101 lines
3.5 KiB
C++
/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* The topology here is configurable; it can be a hierachical (default
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* one) or a 2D torus or a 2D torus with half switches killed. I think
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* all input port has a one-input-one-output switch connected just to
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* control and bandwidth, since we don't control bandwidth on input
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* ports. Basically, the class has a vector of nodes and edges. First
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* 2*m_nodes elements in the node vector are input and output
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* ports. Edges are represented in two vectors of src and dest
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* nodes. All edges have latency.
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*/
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#ifndef __MEM_RUBY_NETWORK_TOPOLOGY_HH__
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#define __MEM_RUBY_NETWORK_TOPOLOGY_HH__
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#include <iostream>
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#include <string>
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#include <vector>
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#include "mem/protocol/LinkDirection.hh"
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#include "mem/ruby/common/TypeDefines.hh"
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#include "mem/ruby/network/BasicLink.hh"
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class NetDest;
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class Network;
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typedef std::vector<std::vector<int> > Matrix;
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struct LinkEntry
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{
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BasicLink *link;
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LinkDirection direction;
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};
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typedef std::map<std::pair<SwitchID, SwitchID>, LinkEntry> LinkMap;
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class Topology
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{
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public:
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Topology(uint32_t num_routers, std::vector<BasicExtLink *> ext_links,
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std::vector<BasicIntLink *> int_links);
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uint32_t numSwitches() const { return m_number_of_switches; }
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void createLinks(Network *net);
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void print(std::ostream& out) const { out << "[Topology]"; }
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protected:
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void addLink(SwitchID src, SwitchID dest, BasicLink* link,
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LinkDirection dir);
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void makeLink(Network *net, SwitchID src, SwitchID dest,
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const NetDest& routing_table_entry);
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NodeID m_nodes;
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uint32_t m_number_of_switches;
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std::vector<BasicExtLink*> m_ext_link_vector;
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std::vector<BasicIntLink*> m_int_link_vector;
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Matrix m_component_latencies;
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Matrix m_component_inter_switches;
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LinkMap m_link_map;
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};
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inline std::ostream&
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operator<<(std::ostream& out, const Topology& obj)
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{
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obj.print(out);
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out << std::flush;
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return out;
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}
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#endif // __MEM_RUBY_NETWORK_TOPOLOGY_HH__
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