6e634beb8a
If we fault, change the state to faulting so that we don't fault again in the same cycle.
412 lines
11 KiB
C++
412 lines
11 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Dave Greene
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* Nathan Binkert
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*/
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#ifndef __CPU_SIMPLE_BASE_HH__
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#define __CPU_SIMPLE_BASE_HH__
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#include "arch/predecoder.hh"
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#include "base/statistics.hh"
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#include "config/full_system.hh"
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#include "config/the_isa.hh"
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#include "cpu/base.hh"
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#include "cpu/pc_event.hh"
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#include "cpu/simple_thread.hh"
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#include "cpu/static_inst.hh"
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#include "mem/packet.hh"
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#include "mem/port.hh"
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#include "mem/request.hh"
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#include "sim/eventq.hh"
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#include "sim/system.hh"
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// forward declarations
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#if FULL_SYSTEM
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class Processor;
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namespace TheISA
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{
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class ITB;
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class DTB;
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}
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class MemObject;
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#else
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class Process;
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#endif // FULL_SYSTEM
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namespace TheISA
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{
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class Predecoder;
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}
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class ThreadContext;
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class Checkpoint;
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namespace Trace {
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class InstRecord;
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}
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class BaseSimpleCPUParams;
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class BaseSimpleCPU : public BaseCPU
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{
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protected:
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typedef TheISA::MiscReg MiscReg;
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typedef TheISA::FloatReg FloatReg;
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typedef TheISA::FloatRegBits FloatRegBits;
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protected:
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Trace::InstRecord *traceData;
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inline void checkPcEventQueue() {
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Addr oldpc, pc = thread->instAddr();
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do {
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oldpc = pc;
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system->pcEventQueue.service(tc);
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pc = thread->instAddr();
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} while (oldpc != pc);
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}
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public:
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void wakeup();
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void zero_fill_64(Addr addr) {
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static int warned = 0;
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if (!warned) {
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warn ("WH64 is not implemented");
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warned = 1;
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}
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};
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public:
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BaseSimpleCPU(BaseSimpleCPUParams *params);
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virtual ~BaseSimpleCPU();
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public:
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/** SimpleThread object, provides all the architectural state. */
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SimpleThread *thread;
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/** ThreadContext object, provides an interface for external
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* objects to modify this thread's state.
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*/
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ThreadContext *tc;
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protected:
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enum Status {
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Idle,
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Running,
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Faulting,
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ITBWaitResponse,
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IcacheRetry,
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IcacheWaitResponse,
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IcacheWaitSwitch,
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DTBWaitResponse,
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DcacheRetry,
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DcacheWaitResponse,
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DcacheWaitSwitch,
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SwitchedOut
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};
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Status _status;
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public:
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#if FULL_SYSTEM
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Addr dbg_vtophys(Addr addr);
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bool interval_stats;
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#endif
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// current instruction
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TheISA::MachInst inst;
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// The predecoder
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TheISA::Predecoder predecoder;
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StaticInstPtr curStaticInst;
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StaticInstPtr curMacroStaticInst;
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//This is the offset from the current pc that fetch should be performed at
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Addr fetchOffset;
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//This flag says to stay at the current pc. This is useful for
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//instructions which go beyond MachInst boundaries.
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bool stayAtPC;
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void checkForInterrupts();
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void setupFetchRequest(Request *req);
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void preExecute();
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void postExecute();
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void advancePC(Fault fault);
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virtual void deallocateContext(int thread_num);
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virtual void haltContext(int thread_num);
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// statistics
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virtual void regStats();
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virtual void resetStats();
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// number of simulated instructions
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Counter numInst;
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Counter startNumInst;
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Stats::Scalar numInsts;
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void countInst()
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{
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numInst++;
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numInsts++;
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system->totalNumInsts++;
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thread->funcExeInst++;
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}
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virtual Counter totalInstructions() const
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{
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return numInst - startNumInst;
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}
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//number of integer alu accesses
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Stats::Scalar numIntAluAccesses;
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//number of float alu accesses
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Stats::Scalar numFpAluAccesses;
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//number of function calls/returns
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Stats::Scalar numCallsReturns;
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//conditional control instructions;
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Stats::Scalar numCondCtrlInsts;
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//number of int instructions
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Stats::Scalar numIntInsts;
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//number of float instructions
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Stats::Scalar numFpInsts;
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//number of integer register file accesses
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Stats::Scalar numIntRegReads;
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Stats::Scalar numIntRegWrites;
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//number of float register file accesses
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Stats::Scalar numFpRegReads;
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Stats::Scalar numFpRegWrites;
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// number of simulated memory references
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Stats::Scalar numMemRefs;
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Stats::Scalar numLoadInsts;
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Stats::Scalar numStoreInsts;
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// number of idle cycles
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Stats::Formula numIdleCycles;
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// number of busy cycles
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Stats::Formula numBusyCycles;
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// number of simulated loads
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Counter numLoad;
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Counter startNumLoad;
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// number of idle cycles
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Stats::Average notIdleFraction;
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Stats::Formula idleFraction;
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// number of cycles stalled for I-cache responses
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Stats::Scalar icacheStallCycles;
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Counter lastIcacheStall;
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// number of cycles stalled for I-cache retries
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Stats::Scalar icacheRetryCycles;
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Counter lastIcacheRetry;
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// number of cycles stalled for D-cache responses
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Stats::Scalar dcacheStallCycles;
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Counter lastDcacheStall;
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// number of cycles stalled for D-cache retries
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Stats::Scalar dcacheRetryCycles;
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Counter lastDcacheRetry;
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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// These functions are only used in CPU models that split
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// effective address computation from the actual memory access.
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void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
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Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n");
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M5_DUMMY_RETURN}
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// The register accessor methods provide the index of the
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// instruction's operand (e.g., 0 or 1), not the architectural
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// register index, to simplify the implementation of register
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// renaming. We find the architectural register index by indexing
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// into the instruction's own operand index table. Note that a
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// raw pointer to the StaticInst is provided instead of a
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// ref-counted StaticInstPtr to redice overhead. This is fine as
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// long as these methods don't copy the pointer into any long-term
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// storage (which is pretty hard to imagine they would have reason
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// to do).
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uint64_t readIntRegOperand(const StaticInst *si, int idx)
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{
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numIntRegReads++;
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return thread->readIntReg(si->srcRegIdx(idx));
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}
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FloatReg readFloatRegOperand(const StaticInst *si, int idx)
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{
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numFpRegReads++;
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int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
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return thread->readFloatReg(reg_idx);
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}
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FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
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{
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numFpRegReads++;
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int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
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return thread->readFloatRegBits(reg_idx);
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}
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void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
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{
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numIntRegWrites++;
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thread->setIntReg(si->destRegIdx(idx), val);
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}
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void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
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{
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numFpRegWrites++;
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int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
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thread->setFloatReg(reg_idx, val);
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}
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void setFloatRegOperandBits(const StaticInst *si, int idx,
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FloatRegBits val)
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{
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numFpRegWrites++;
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int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
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thread->setFloatRegBits(reg_idx, val);
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}
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bool readPredicate() { return thread->readPredicate(); }
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void setPredicate(bool val)
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{
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thread->setPredicate(val);
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if (traceData) {
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traceData->setPredicate(val);
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}
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}
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TheISA::PCState pcState() { return thread->pcState(); }
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void pcState(const TheISA::PCState &val) { thread->pcState(val); }
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Addr instAddr() { return thread->instAddr(); }
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Addr nextInstAddr() { return thread->nextInstAddr(); }
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MicroPC microPC() { return thread->microPC(); }
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MiscReg readMiscRegNoEffect(int misc_reg)
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{
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return thread->readMiscRegNoEffect(misc_reg);
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}
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MiscReg readMiscReg(int misc_reg)
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{
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numIntRegReads++;
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return thread->readMiscReg(misc_reg);
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}
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void setMiscReg(int misc_reg, const MiscReg &val)
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{
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numIntRegWrites++;
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return thread->setMiscReg(misc_reg, val);
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}
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MiscReg readMiscRegOperand(const StaticInst *si, int idx)
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{
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numIntRegReads++;
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int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
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return thread->readMiscReg(reg_idx);
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}
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void setMiscRegOperand(
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const StaticInst *si, int idx, const MiscReg &val)
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{
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numIntRegWrites++;
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int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
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return thread->setMiscReg(reg_idx, val);
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}
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void demapPage(Addr vaddr, uint64_t asn)
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{
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thread->demapPage(vaddr, asn);
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}
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void demapInstPage(Addr vaddr, uint64_t asn)
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{
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thread->demapInstPage(vaddr, asn);
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}
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void demapDataPage(Addr vaddr, uint64_t asn)
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{
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thread->demapDataPage(vaddr, asn);
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}
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unsigned readStCondFailures() {
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return thread->readStCondFailures();
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}
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void setStCondFailures(unsigned sc_failures) {
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thread->setStCondFailures(sc_failures);
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}
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MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID)
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{
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panic("Simple CPU models do not support multithreaded "
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"register access.\n");
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}
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void setRegOtherThread(int regIdx, const MiscReg &val,
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ThreadID tid = InvalidThreadID)
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{
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panic("Simple CPU models do not support multithreaded "
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"register access.\n");
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}
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//Fault CacheOp(uint8_t Op, Addr EA);
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#if FULL_SYSTEM
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Fault hwrei() { return thread->hwrei(); }
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bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
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#else
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void syscall(int64_t callnum) { thread->syscall(callnum); }
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#endif
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bool misspeculating() { return thread->misspeculating(); }
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ThreadContext *tcBase() { return tc; }
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};
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#endif // __CPU_SIMPLE_BASE_HH__
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