Update stats for recent changes. Mostly minor changes in register access stats due to addition of new cc register type and slightly different (and more accurate) classification of int vs. fp register accesses.
21 lines
750 B
Text
Executable file
21 lines
750 B
Text
Executable file
gem5 Simulator System. http://gem5.org
|
|
gem5 is copyrighted software; use the --copyright option for details.
|
|
|
|
gem5 compiled Oct 16 2013 01:31:26
|
|
gem5 started Oct 16 2013 01:35:23
|
|
gem5 executing on zizzer
|
|
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing
|
|
Global frequency set at 1000000000000 ticks per second
|
|
info: Entering event queue @ 0. Starting simulation...
|
|
Begining test of difficult SPARC instructions...
|
|
LDSTUB: Passed
|
|
SWAP: Passed
|
|
CAS FAIL: Passed
|
|
CAS WORK: Passed
|
|
CASX FAIL: Passed
|
|
CASX WORK: Passed
|
|
LDTX: Passed
|
|
LDTW: Passed
|
|
STTW: Passed
|
|
Done
|
|
Exiting @ tick 26524500 because target called exit()
|