932 lines
106 KiB
Plaintext
932 lines
106 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.074220 # Number of seconds simulated
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sim_ticks 74219948500 # Number of ticks simulated
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final_tick 74219948500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 84730 # Simulator instruction rate (inst/s)
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host_op_rate 92772 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 36497737 # Simulator tick rate (ticks/s)
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host_mem_usage 298520 # Number of bytes of host memory used
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host_seconds 2033.55 # Real time elapsed on the host
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sim_insts 172303021 # Number of instructions simulated
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sim_ops 188656503 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 131072 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 111680 # Number of bytes read from this memory
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system.physmem.bytes_read::total 242752 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 131072 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 131072 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 2048 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 1745 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 3793 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1765994 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 1504717 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 3270711 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1765994 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1765994 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1765994 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 1504717 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 3270711 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 3794 # Number of read requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.readBursts 3794 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 242816 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 242816 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 306 # Per bank write bursts
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system.physmem.perBankRdBursts::1 215 # Per bank write bursts
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system.physmem.perBankRdBursts::2 133 # Per bank write bursts
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system.physmem.perBankRdBursts::3 308 # Per bank write bursts
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system.physmem.perBankRdBursts::4 298 # Per bank write bursts
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system.physmem.perBankRdBursts::5 299 # Per bank write bursts
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system.physmem.perBankRdBursts::6 264 # Per bank write bursts
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system.physmem.perBankRdBursts::7 216 # Per bank write bursts
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system.physmem.perBankRdBursts::8 246 # Per bank write bursts
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system.physmem.perBankRdBursts::9 215 # Per bank write bursts
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system.physmem.perBankRdBursts::10 289 # Per bank write bursts
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system.physmem.perBankRdBursts::11 193 # Per bank write bursts
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system.physmem.perBankRdBursts::12 189 # Per bank write bursts
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system.physmem.perBankRdBursts::13 206 # Per bank write bursts
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system.physmem.perBankRdBursts::14 217 # Per bank write bursts
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system.physmem.perBankRdBursts::15 200 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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system.physmem.perBankWrBursts::3 0 # Per bank write bursts
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system.physmem.perBankWrBursts::4 0 # Per bank write bursts
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system.physmem.perBankWrBursts::5 0 # Per bank write bursts
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system.physmem.perBankWrBursts::6 0 # Per bank write bursts
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system.physmem.perBankWrBursts::7 0 # Per bank write bursts
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system.physmem.perBankWrBursts::8 0 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 0 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 0 # Per bank write bursts
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system.physmem.perBankWrBursts::13 0 # Per bank write bursts
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system.physmem.perBankWrBursts::14 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 74219930000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 3794 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 2825 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 784 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 142 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 717 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 334.192469 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 180.652659 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 576.534776 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::64-65 257 35.84% 35.84% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-129 120 16.74% 52.58% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::192-193 71 9.90% 62.48% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-257 49 6.83% 69.32% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::320-321 19 2.65% 71.97% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-385 26 3.63% 75.59% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::448-449 20 2.79% 78.38% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-513 17 2.37% 80.75% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::576-577 17 2.37% 83.12% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-641 40 5.58% 88.70% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::704-705 17 2.37% 91.07% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-769 6 0.84% 91.91% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::832-833 6 0.84% 92.75% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-897 8 1.12% 93.86% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::960-961 6 0.84% 94.70% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1025 5 0.70% 95.40% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1088-1089 4 0.56% 95.96% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1152-1153 1 0.14% 96.09% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1216-1217 2 0.28% 96.37% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1280-1281 2 0.28% 96.65% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1344-1345 2 0.28% 96.93% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1408-1409 2 0.28% 97.21% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1472-1473 1 0.14% 97.35% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1536-1537 1 0.14% 97.49% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1600-1601 1 0.14% 97.63% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1664-1665 1 0.14% 97.77% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1728-1729 1 0.14% 97.91% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1792-1793 2 0.28% 98.19% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1856-1857 1 0.14% 98.33% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1984-1985 2 0.28% 98.61% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2176-2177 1 0.14% 98.74% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2688-2689 1 0.14% 98.88% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2816-2817 1 0.14% 99.02% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3008-3009 1 0.14% 99.16% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3200-3201 1 0.14% 99.30% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3392-3393 1 0.14% 99.44% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3648-3649 1 0.14% 99.58% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3712-3713 1 0.14% 99.72% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::6656-6657 1 0.14% 99.86% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::8192-8193 1 0.14% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 717 # Bytes accessed per row activation
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system.physmem.totQLat 25203500 # Total ticks spent queuing
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system.physmem.totMemAccLat 100713500 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 18970000 # Total ticks spent in databus transfers
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system.physmem.totBankLat 56540000 # Total ticks spent accessing banks
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system.physmem.avgQLat 6642.99 # Average queueing delay per DRAM burst
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system.physmem.avgBankLat 14902.48 # Average bank access latency per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 26545.47 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 3.27 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 3.27 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 0.03 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
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system.physmem.readRowHits 3077 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 81.10 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 19562448.60 # Average gap between requests
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system.physmem.pageHitRate 81.10 # Row buffer hit rate, read and write combined
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system.physmem.prechargeAllPercent 0.24 # Percentage of time for which DRAM has all the banks in precharge state
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system.membus.throughput 3270711 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 2723 # Transaction distribution
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system.membus.trans_dist::ReadResp 2722 # Transaction distribution
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system.membus.trans_dist::ReadExReq 1071 # Transaction distribution
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system.membus.trans_dist::ReadExResp 1071 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7587 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 7587 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 242752 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 242752 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 242752 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 4682500 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
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system.membus.respLayer1.occupancy 35532750 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
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system.cpu.branchPred.lookups 94784274 # Number of BP lookups
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system.cpu.branchPred.condPredicted 74784006 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 6281562 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 44678423 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 43050018 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 96.355276 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 4356639 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 88400 # Number of incorrect RAS predictions.
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 400 # Number of system calls
|
|
system.cpu.numCycles 148439898 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 39656921 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 380179930 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 94784274 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 47406657 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 80370665 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 27283127 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.BlockedCycles 7220968 # Number of cycles fetch has spent blocked
|
|
system.cpu.fetch.MiscStallCycles 44 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 6188 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 50 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 36850894 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 1831983 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 148240577 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 2.801601 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 3.152871 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 68038757 45.90% 45.90% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 5265463 3.55% 49.45% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 10540668 7.11% 56.56% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 10285704 6.94% 63.50% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 8660470 5.84% 69.34% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 6545129 4.42% 73.76% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 6246382 4.21% 77.97% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 8002830 5.40% 83.37% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 24655174 16.63% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 148240577 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.638536 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 2.561171 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 45513795 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 5886752 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 74804124 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 1203493 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 20832413 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 14327914 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 164349 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 392779880 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 733794 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 20832413 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 50900748 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 730699 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 603191 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 70558309 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 4615217 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 371308082 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 339275 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 3661219 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.FullRegisterEvents 231 # Number of times there has been no free registers
|
|
system.cpu.rename.RenamedOperands 631703471 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 1581699910 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 1506871257 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 3203425 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 333659332 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 25072 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 25068 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 13010245 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 43012682 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 16416405 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 5733542 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 3666500 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 329190147 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 47154 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 249456617 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 789368 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 139503392 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 362002773 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 1938 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 148240577 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.682782 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.761427 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 56059832 37.82% 37.82% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 22638796 15.27% 53.09% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 24824164 16.75% 69.83% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 20343400 13.72% 83.56% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 12534797 8.46% 92.01% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 6516114 4.40% 96.41% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 4026095 2.72% 99.12% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 1116067 0.75% 99.88% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 181312 0.12% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 148240577 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 965215 38.57% 38.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 5593 0.22% 38.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 38.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 38.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 38.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 38.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 101 0.00% 38.80% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.80% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.80% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.80% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.80% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.80% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.80% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.80% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.80% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 1158967 46.31% 85.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 372730 14.89% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 194899963 78.13% 78.13% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 979613 0.39% 78.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 33082 0.01% 78.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 164367 0.07% 78.60% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 255141 0.10% 78.70% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 76420 0.03% 78.73% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 466123 0.19% 78.92% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 206380 0.08% 79.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 71866 0.03% 79.03% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 38355278 15.38% 94.41% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 13948063 5.59% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 249456617 # Type of FU issued
|
|
system.cpu.iq.rate 1.680523 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 2502654 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.010032 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 646705826 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 466563414 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 237885445 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 3740007 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 2195697 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 1842613 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 250082852 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 1876419 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 2013198 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 13163198 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 11604 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 18881 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 3771771 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 18 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 107 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 20832413 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 18550 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 893 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 329254497 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 785294 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 43012682 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 16416405 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 24746 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 188 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 276 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 18881 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 3889958 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 3760086 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 7650044 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 242960519 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 36851938 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 6496098 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 17196 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 50500394 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 53426072 # Number of branches executed
|
|
system.cpu.iew.exec_stores 13648456 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.636760 # Inst execution rate
|
|
system.cpu.iew.wb_sent 240785663 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 239728058 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 148474078 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 267261470 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.614984 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.555539 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 140583609 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 6128235 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 127408164 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.480838 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.185451 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 57701829 45.29% 45.29% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 31696937 24.88% 70.17% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 13777780 10.81% 80.98% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 7640618 6.00% 86.98% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 4387787 3.44% 90.42% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 1321958 1.04% 91.46% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 1703212 1.34% 92.80% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 1308014 1.03% 93.82% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 7870029 6.18% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 127408164 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 172317409 # Number of instructions committed
|
|
system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 42494118 # Number of memory references committed
|
|
system.cpu.commit.loads 29849484 # Number of loads committed
|
|
system.cpu.commit.membars 22408 # Number of memory barriers committed
|
|
system.cpu.commit.branches 40300311 # Number of branches committed
|
|
system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 150106217 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 1848934 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 7870029 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 448787434 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 679451113 # The number of ROB writes
|
|
system.cpu.timesIdled 2805 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 199321 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 172303021 # Number of Instructions Simulated
|
|
system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.861505 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.861505 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.160759 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.160759 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 1079417004 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 384871783 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 2913086 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 2499105 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 54501288 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 820036 # number of misc regfile writes
|
|
system.cpu.toL2Bus.throughput 5169500 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 4899 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 4898 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 18 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 1079 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 1079 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8251 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3722 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 11973 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 264000 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119680 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 383680 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 383680 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 3016000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 6552496 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 3047739 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.icache.tags.replacements 2394 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 1347.740549 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 36845557 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 4125 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 8932.256242 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1347.740549 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.658076 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.658076 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 36845557 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 36845557 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 36845557 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 36845557 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 36845557 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 36845557 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 5337 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 5337 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 5337 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 5337 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 5337 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 5337 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 225938245 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 225938245 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 225938245 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 225938245 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 225938245 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 225938245 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 36850894 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 36850894 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 36850894 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 36850894 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 36850894 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 36850894 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000145 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42334.316095 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 42334.316095 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 42334.316095 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 42334.316095 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 42334.316095 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 42334.316095 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 1128 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 59.368421 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1211 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 1211 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 1211 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 1211 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 1211 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 1211 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4126 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 4126 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 4126 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 4126 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 4126 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 4126 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168088504 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 168088504 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168088504 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 168088504 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168088504 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 168088504 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000112 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40738.852157 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40738.852157 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40738.852157 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 40738.852157 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40738.852157 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 40738.852157 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 1967.449764 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 2162 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 2732 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 0.791362 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 4.994098 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1425.569687 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 536.885979 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043505 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.016384 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.060042 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 2073 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 88 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 2161 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 2073 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 96 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2169 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 2073 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 96 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2169 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 2053 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 685 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 2738 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 1071 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 1071 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 2053 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 1756 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 3809 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 2053 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 1756 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 3809 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143225500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51383000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 194608500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 72292250 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 72292250 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 143225500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 123675250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 266900750 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 143225500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 123675250 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 266900750 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 4126 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 773 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 4899 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1079 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 1079 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 4126 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1852 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 5978 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 4126 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1852 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 5978 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.497576 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.886158 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.558890 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992586 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.992586 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.497576 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.948164 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.637170 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.497576 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.948164 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.637170 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69764.003897 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75011.678832 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 71076.880935 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67499.766573 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67499.766573 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69764.003897 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70430.096811 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 70071.081649 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69764.003897 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70430.096811 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 70071.081649 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 11 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 15 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 11 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 11 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2049 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 674 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 2723 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1071 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 1071 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2049 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 1745 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 3794 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2049 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 1745 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 3794 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117253000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42297000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159550000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 58841750 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 58841750 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117253000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101138750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 218391750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117253000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101138750 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 218391750 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871928 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.555828 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992586 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992586 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942225 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.634660 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942225 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.634660 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57224.499756 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62755.192878 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58593.463092 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54940.943044 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54940.943044 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57224.499756 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57959.169054 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57562.401160 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57224.499756 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57959.169054 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57562.401160 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 57 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 1406.103135 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 46786156 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 1852 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 25262.503240 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 1406.103135 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.343287 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.343287 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 34384711 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 34384711 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 12356564 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 12356564 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 22474 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 22474 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 46741275 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 46741275 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 46741275 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 46741275 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1902 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1902 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 7723 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 7723 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 9625 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 9625 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 9625 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 9625 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 121862727 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 121862727 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 465623746 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 465623746 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 587486473 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 587486473 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 587486473 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 587486473 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 34386613 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 34386613 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22476 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 22476 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 46750900 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 46750900 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 46750900 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 46750900 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64070.834385 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 64070.834385 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60290.527774 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 60290.527774 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 61037.555636 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 61037.555636 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 61037.555636 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 61037.555636 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 592 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 314 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.818182 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 78.500000 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 18 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 18 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1128 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 1128 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6645 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 6645 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 7773 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 7773 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 7773 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 7773 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 774 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 774 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1078 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 1078 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1852 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1852 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1852 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1852 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53113761 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 53113761 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73393498 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 73393498 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126507259 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 126507259 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126507259 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 126507259 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68622.430233 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68622.430233 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68083.022263 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68083.022263 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68308.455184 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 68308.455184 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68308.455184 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 68308.455184 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|