b63631536d
This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
436 lines
49 KiB
Plaintext
436 lines
49 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.118729 # Number of seconds simulated
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sim_ticks 118729316000 # Number of ticks simulated
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final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 2022504 # Simulator instruction rate (inst/s)
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host_op_rate 2022504 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2612866318 # Simulator tick rate (ticks/s)
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host_mem_usage 228676 # Number of bytes of host memory used
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host_seconds 45.44 # Real time elapsed on the host
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sim_insts 91903056 # Number of instructions simulated
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sim_ops 91903056 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory
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system.physmem.bytes_read::total 304960 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 167744 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 167744 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 2621 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 4765 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1412827 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 1155704 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 2568532 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1412827 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1412827 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1412827 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 1155704 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 2568532 # Total bandwidth to/from this memory (bytes/s)
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system.membus.throughput 2568532 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 3043 # Transaction distribution
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system.membus.trans_dist::ReadResp 3043 # Transaction distribution
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system.membus.trans_dist::ReadExReq 1722 # Transaction distribution
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system.membus.trans_dist::ReadExResp 1722 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9530 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 9530 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 304960 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
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system.membus.respLayer1.occupancy 42885000 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 19996198 # DTB read hits
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system.cpu.dtb.read_misses 10 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 19996208 # DTB read accesses
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system.cpu.dtb.write_hits 6501103 # DTB write hits
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system.cpu.dtb.write_misses 23 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 6501126 # DTB write accesses
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system.cpu.dtb.data_hits 26497301 # DTB hits
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system.cpu.dtb.data_misses 33 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 26497334 # DTB accesses
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system.cpu.itb.fetch_hits 91903090 # ITB hits
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system.cpu.itb.fetch_misses 47 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 91903137 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 389 # Number of system calls
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system.cpu.numCycles 237458632 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 91903056 # Number of instructions committed
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system.cpu.committedOps 91903056 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses
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system.cpu.num_func_calls 2059216 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls
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system.cpu.num_int_insts 79581109 # number of integer instructions
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system.cpu.num_fp_insts 6862064 # number of float instructions
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system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read
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system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written
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system.cpu.num_mem_refs 26497334 # number of memory refs
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system.cpu.num_load_insts 19996208 # Number of load instructions
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system.cpu.num_store_insts 6501126 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 237458632 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.tags.replacements 6681 # number of replacements
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system.cpu.icache.tags.tagsinuse 1418.052773 # Cycle average of tags in use
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system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks.
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system.cpu.icache.tags.sampled_refs 8510 # Sample count of references to valid blocks.
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system.cpu.icache.tags.avg_refs 10798.423032 # Average number of references to valid blocks.
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system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.tags.occ_blocks::cpu.inst 1418.052773 # Average occupied blocks per requestor
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system.cpu.icache.tags.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy
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system.cpu.icache.tags.occ_percent::total 0.692409 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 91894580 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 91894580 # number of overall hits
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system.cpu.icache.overall_hits::total 91894580 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 8510 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 8510 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 8510 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses
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system.cpu.icache.overall_misses::total 8510 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 220712000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 220712000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 220712000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 220712000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 220712000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 220712000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 91903090 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 91903090 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 91903090 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25935.605170 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total 25935.605170 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 25935.605170 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total 25935.605170 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 25935.605170 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total 25935.605170 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8510 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 8510 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 8510 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 203692000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 203692000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 203692000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 203692000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 203692000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 203692000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000093 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_miss_rate::total 0.000093 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_miss_rate::total 0.000093 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23935.605170 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23935.605170 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.tags.replacements 0 # number of replacements
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system.cpu.l2cache.tags.tagsinuse 2074.070560 # Cycle average of tags in use
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system.cpu.l2cache.tags.total_refs 5956 # Total number of references to valid blocks.
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system.cpu.l2cache.tags.sampled_refs 3109 # Sample count of references to valid blocks.
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system.cpu.l2cache.tags.avg_refs 1.915729 # Average number of references to valid blocks.
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system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.tags.occ_blocks::writebacks 17.795178 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_blocks::cpu.inst 1705.018003 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_blocks::cpu.data 351.257379 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052033 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::cpu.data 0.010720 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::total 0.063296 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.inst 5889 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::total 5942 # number of ReadReq hits
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system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits
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system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits
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system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
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system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
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system.cpu.l2cache.demand_hits::cpu.inst 5889 # number of demand (read+write) hits
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system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits
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system.cpu.l2cache.demand_hits::total 5968 # number of demand (read+write) hits
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system.cpu.l2cache.overall_hits::cpu.inst 5889 # number of overall hits
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system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits
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system.cpu.l2cache.overall_hits::total 5968 # number of overall hits
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system.cpu.l2cache.ReadReq_misses::cpu.inst 2621 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::total 3043 # number of ReadReq misses
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system.cpu.l2cache.ReadExReq_misses::cpu.data 1722 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_misses::total 1722 # number of ReadExReq misses
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system.cpu.l2cache.demand_misses::cpu.inst 2621 # number of demand (read+write) misses
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system.cpu.l2cache.demand_misses::cpu.data 2144 # number of demand (read+write) misses
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system.cpu.l2cache.demand_misses::total 4765 # number of demand (read+write) misses
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system.cpu.l2cache.overall_misses::cpu.inst 2621 # number of overall misses
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system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses
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system.cpu.l2cache.overall_misses::total 4765 # number of overall misses
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system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 136292000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21944000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_latency::total 158236000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 89544000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::total 89544000 # number of ReadExReq miss cycles
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system.cpu.l2cache.demand_miss_latency::cpu.inst 136292000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_latency::cpu.data 111488000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_latency::total 247780000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.inst 136292000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.data 111488000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_latency::total 247780000 # number of overall miss cycles
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system.cpu.l2cache.ReadReq_accesses::cpu.inst 8510 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::total 8985 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.demand_accesses::cpu.inst 8510 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::total 10733 # number of demand (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.inst 8510 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_accesses::total 10733 # number of overall (read+write) accesses
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system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.307991 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_miss_rate::total 0.338676 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses
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system.cpu.l2cache.demand_miss_rate::cpu.inst 0.307991 # miss rate for demand accesses
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system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses
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system.cpu.l2cache.demand_miss_rate::total 0.443958 # miss rate for demand accesses
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|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.307991 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.443958 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2621 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 422 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 3043 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1722 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 1722 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2621 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 2144 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 4765 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2621 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 4765 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104840000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16880000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 121720000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 68880000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 68880000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104840000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85760000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 190600000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104840000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85760000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 190600000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.338676 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.443958 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.443958 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 157 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 1442.043392 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 1442.043392 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.352061 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 6499355 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 26495078 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 26495078 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 26495078 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 26495078 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 475 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 475 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1748 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1748 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 2223 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 2223 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 23899000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 23899000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 95048000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 95048000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 118947000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 118947000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 118947000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 118947000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50313.684211 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 50313.684211 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54375.286041 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 54375.286041 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 53507.422402 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 53507.422402 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 107 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22949000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 22949000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91552000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 91552000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114501000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 114501000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114501000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 114501000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48313.684211 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48313.684211 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52375.286041 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52375.286041 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.throughput 5843207 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 8985 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17020 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4553 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 21573 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 544640 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 693760 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 693760 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 5527000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 12765000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|