gem5/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
Andreas Hansson 74553c7d3f stats: Update the stats to reflect bus and memory changes
This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.
2013-05-30 12:54:18 -04:00

105 lines
11 KiB
Text

---------- Begin Simulation Statistics ----------
sim_seconds 0.290499 # Number of seconds simulated
sim_ticks 290498967000 # Number of ticks simulated
final_tick 290498967000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1591705 # Simulator instruction rate (inst/s)
host_op_rate 1794011 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 912762441 # Simulator tick rate (ticks/s)
host_mem_usage 237748 # Number of bytes of host memory used
host_seconds 318.26 # Real time elapsed on the host
sim_insts 506581607 # Number of instructions simulated
sim_ops 570968167 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 2066445500 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 422852701 # Number of bytes read from this memory
system.physmem.bytes_read::total 2489298201 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 2066445500 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 2066445500 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 216067624 # Number of bytes written to this memory
system.physmem.bytes_written::total 216067624 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 516611375 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 125228857 # Number of read requests responded to by this memory
system.physmem.num_reads::total 641840232 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 55727847 # Number of write requests responded to by this memory
system.physmem.num_writes::total 55727847 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7113434933 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1455608278 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 8569043211 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7113434933 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7113434933 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 743781041 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 743781041 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7113434933 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2199389318 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9312824252 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 9312824252 # Throughput (bytes/s)
system.membus.data_through_bus 2705365825 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
system.cpu.numCycles 580997935 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 506581607 # Number of instructions committed
system.cpu.committedOps 570968167 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 470727695 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 19311615 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 94895872 # number of instructions that are conditional controls
system.cpu.num_int_insts 470727695 # number of integer instructions
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 2465023683 # number of times the integer registers were read
system.cpu.num_int_register_writes 646169352 # number of times the integer registers were written
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 182890034 # number of memory refs
system.cpu.num_load_insts 126029555 # Number of load instructions
system.cpu.num_store_insts 56860479 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 580997935 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------