cf94242539
put back in Tcc code that was deleted in last merge
arch/sparc/isa/bitfields.isa:
clean up condition codes a little bit
--HG--
extra : convert_revision : c554fd5c3ee8cfd6643f69f8351124a7a4b5d9fa
648 lines
29 KiB
Text
648 lines
29 KiB
Text
////////////////////////////////////////////////////////////////////
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//
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// The actual decoder specification
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//
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decode OP default Unknown::unknown()
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{
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0x0: decode OP2
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{
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//Throw an illegal instruction acception
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0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
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0x1: Branch::bpcc({{
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switch(BPCC)
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{
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case 1:
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case 3:
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fault = new IllegalInstruction;
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case 0:
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if(passesCondition(CcrIcc, COND2))
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;//branchHere
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break;
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case 2:
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if(passesCondition(CcrXcc, COND2))
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;//branchHere
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break;
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}
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}});//BPcc
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0x2: Branch::bicc({{
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if(passesCondition(CcrIcc, COND2))
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;//branchHere
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}});//Bicc
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0x3: Branch::bpr({{
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switch(RCOND2)
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{
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case 0:
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case 4:
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fault = new IllegalInstruction;
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case 1:
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if(Rs1 == 0)
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;//branchHere
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break;
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case 2:
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if(Rs1 <= 0)
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;//branchHere
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break;
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case 3:
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if(Rs1 < 0)
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;//branchHere
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break;
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case 5:
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if(Rs1 != 0)
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;//branchHere
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break;
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case 6:
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if(Rs1 > 0)
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;//branchHere
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break;
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case 7:
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if(Rs1 >= 0)
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;//branchHere
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break;
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}
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}}); //BPr
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//SETHI (or NOP if rd == 0 and imm == 0)
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0x4: IntegerOp::sethi({{Rd = (IMM22 << 10) & 0xFFFFFC00;}});
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0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
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0x6: Trap::fbfcc({{fault = new FpDisabled;}});
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}
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0x1: Branch::call({{
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//branch here
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Rd = xc->pc;
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}});
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0x2: decode OP3 {
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format IntegerOp {
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0x00: add({{
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int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
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Rd = Rs1.sdw + val2;
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}});//ADD
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0x01: and({{
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uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
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Rd = Rs1.udw & val2;
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}});//AND
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0x02: or({{
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uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
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Rd = Rs1.udw | val2;
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}});//OR
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0x03: xor({{
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uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
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Rd = Rs1.udw ^ val2;
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}});//XOR
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0x04: sub({{
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int64_t val2 = ~((uint64_t)(I ? SIMM13.sdw : Rs2.udw))+1;
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Rd = Rs1.sdw + val2;
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}});//SUB
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0x05: andn({{
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uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
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Rd = Rs1.udw & ~val2;
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}});//ANDN
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0x06: orn({{
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uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
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Rd = Rs1.udw | ~val2;
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}});//ORN
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0x07: xnor({{
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uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
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Rd = ~(Rs1.udw ^ val2);
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}});//XNOR
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0x08: addc({{
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int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
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int64_t carryin = CcrIccC;
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Rd = Rs1.sdw + val2 + carryin;
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}});//ADDC
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0x09: mulx({{
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int64_t val2 = (I ? SIMM13.sdw : Rs2);
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Rd = Rs1 * val2;
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}});//MULX
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0x0A: umul({{
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uint64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2.udw);
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Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
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YValue = resTemp<63:32>;
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}});//UMUL
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0x0B: smul({{
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int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2.sdw);
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rd.sdw = resTemp = Rs1.sdw<31:0> * val2<31:0>;
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YValue = resTemp<63:32>;
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}});//SMUL
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0x0C: subc({{
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int64_t val2 = ~((int64_t)(I ? SIMM13.sdw : Rs2.sdw))+1;
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int64_t carryin = CcrIccC;
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Rd.sdw = Rs1.sdw + val2 + carryin;
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}});//SUBC
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0x0D: udivx({{
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uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
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if(val2 == 0) fault = new DivisionByZero;
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else Rd.udw = Rs1.udw / val2;
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}});//UDIVX
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0x0E: udiv({{
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uint32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>);
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if(val2 == 0)
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fault = new DivisionByZero;
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resTemp = (uint64_t)((YValue << 32)
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| Rs1.udw<31:0>) / val2;
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int32_t overflow = (resTemp<63:32> != 0);
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if(overflow)
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rd.udw = resTemp = 0xFFFFFFFF;
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else
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rd.udw = resTemp;
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}}); //UDIV
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0x0F: sdiv({{
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int32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>);
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if(val2 == 0)
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fault = new DivisionByZero;
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Rd.sdw = (int64_t)((YValue << 32) |
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Rs1.sdw<31:0>) / val2;
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resTemp = Rd.sdw;
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int32_t overflow = (resTemp<63:31> != 0);
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int32_t underflow =
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(resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
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if(overflow)
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rd.udw = resTemp = 0x7FFFFFFF;
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else if(underflow)
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rd.udw = resTemp = 0xFFFFFFFF80000000;
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else
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rd.udw = resTemp;
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}});//SDIV
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}
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format IntegerOpCc {
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0x10: addcc({{
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int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
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Rd = resTemp = Rs1 + val2;}},
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{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
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{{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
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{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
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{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
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);//ADDcc
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0x11: andcc({{
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int64_t val2 = (I ? SIMM13.sdw : Rs2);
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Rd = Rs1 & val2;}},
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{{0}},{{0}},{{0}},{{0}});//ANDcc
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0x12: orcc({{
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int64_t val2 = (I ? SIMM13.sdw : Rs2);
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Rd = Rs1 | val2;}},
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{{0}},{{0}},{{0}},{{0}});//ORcc
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0x13: xorcc({{
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int64_t val2 = (I ? SIMM13.sdw : Rs2);
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Rd = Rs1 ^ val2;}},
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{{0}},{{0}},{{0}},{{0}});//XORcc
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0x14: subcc({{
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int64_t resTemp, val2 = (int64_t)(I ? SIMM13.sdw : Rs2);
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Rd = resTemp = Rs1 - val2;}},
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{{((Rs1 & 0xFFFFFFFF + (~val2) & 0xFFFFFFFF + 1) >> 31)}},
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{{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
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{{((Rs1 >> 1) + (~val2) >> 1) +
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((Rs1 | ~val2) & 0x1))<63:>}},
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{{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
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);//SUBcc
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0x15: andncc({{
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int64_t val2 = (I ? SIMM13.sdw : Rs2);
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Rd = Rs1 & ~val2;}},
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{{0}},{{0}},{{0}},{{0}});//ANDNcc
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0x16: orncc({{
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int64_t val2 = (I ? SIMM13.sdw : Rs2);
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Rd = Rs1 | ~val2;}},
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{{0}},{{0}},{{0}},{{0}});//ORNcc
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0x17: xnorcc({{
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int64_t val2 = (I ? SIMM13.sdw : Rs2);
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Rd = ~(Rs1 ^ val2);}},
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{{0}},{{0}},{{0}},{{0}});//XNORcc
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0x18: addccc({{
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int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
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int64_t carryin = CcrIccC;
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Rd = resTemp = Rs1 + val2 + carryin;}},
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{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31
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+ carryin)}},
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{{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
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{{((Rs1 >> 1) + (val2 >> 1) +
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((Rs1 & val2) | (carryin & (Rs1 | val2)) & 0x1))<63:>}},
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{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
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);//ADDCcc
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0x1A: umulcc({{
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uint64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
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Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
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YValue = resTemp<63:32>;}},
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{{0}},{{0}},{{0}},{{0}});//UMULcc
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0x1B: smulcc({{
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int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
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Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>;
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YValue = resTemp<63:32>;}}
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,{{0}},{{0}},{{0}},{{0}});//SMULcc
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0x1C: subccc({{
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int64_t resTemp, val2 = (int64_t)(I ? SIMM13.sdw : Rs2);
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int64_t carryin = CcrIccC;
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Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}},
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{{((Rs1 & 0xFFFFFFFF + (~(val2 + carryin)) & 0xFFFFFFFF + 1) >> 31)}},
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{{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
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{{((Rs1 >> 1) + (~(val2 + carryin)) >> 1) + ((Rs1 | ~(val2+carryin)) & 0x1))<63:>}},
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{{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
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);//SUBCcc
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0x1D: udivxcc({{
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uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
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if(val2 == 0) fault = new DivisionByZero;
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else Rd.udw = Rs1.udw / val2;}}
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,{{0}},{{0}},{{0}},{{0}});//UDIVXcc
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0x1E: udivcc({{
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uint32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>);
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if(val2 == 0) fault = new DivisionByZero;
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else
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{
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resTemp = (uint64_t)((YValue << 32) | Rs1.udw<31:0>) / val2;
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int32_t overflow = (resTemp<63:32> != 0);
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if(overflow) rd.udw = resTemp = 0xFFFFFFFF;
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else rd.udw = resTemp;
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} }},
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{{0}},
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{{overflow}},
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{{0}},
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{{0}}
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);//UDIVcc
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0x1F: sdivcc({{
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int32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>);
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if(val2 == 0) fault = new DivisionByZero;
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else
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{
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Rd.sdw = resTemp = (int64_t)((YValue << 32) | Rs1.sdw<31:0>) / val2;
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int32_t overflow = (resTemp<63:31> != 0);
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int32_t underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
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if(overflow) rd.udw = resTemp = 0x7FFFFFFF;
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else if(underflow) rd.udw = resTemp = 0xFFFFFFFF80000000;
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else rd.udw = resTemp;
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} }},
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{{0}},
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{{overflow || underflow}},
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{{0}},
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{{0}}
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);//SDIVcc
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0x20: taddcc({{
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int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
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Rd = resTemp = Rs1 + val2;
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int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
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{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
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{{overflow}},
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{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
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{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
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);//TADDcc
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0x21: tsubcc({{
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int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
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Rd = resTemp = Rs1 + val2;
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int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
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{{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
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{{overflow}},
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{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
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{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
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);//TSUBcc
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0x22: taddcctv({{
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int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
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Rd = resTemp = Rs1 + val2;
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int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
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if(overflow) fault = new TagOverflow;}},
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{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
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{{overflow}},
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{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
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{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
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);//TADDccTV
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0x23: tsubcctv({{
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int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
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Rd = resTemp = Rs1 + val2;
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int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
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if(overflow) fault = new TagOverflow;}},
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{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
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{{overflow}},
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{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
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{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
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);//TSUBccTV
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0x24: mulscc({{
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int64_t resTemp, multiplicand = (I ? SIMM13.sdw : Rs2);
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int32_t multiplier = Rs1<31:0>;
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int32_t savedLSB = Rs1<0:>;
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multiplier = multipler<31:1> |
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((CcrIccN
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^ CcrIccV) << 32);
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if(!YValue<0:>)
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multiplicand = 0;
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Rd = resTemp = multiplicand + multiplier;
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YValue = YValue<31:1> | (savedLSB << 31);}},
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{{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}},
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{{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
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{{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
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{{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
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);//MULScc
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}
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format IntegerOp
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{
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0x25: decode X {
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0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); //SLL
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0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); //SLLX
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}
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0x26: decode X {
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0x0: srl({{Rd = Rs1.udw<31:0> >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRL
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0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRLX
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}
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0x27: decode X {
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0x0: sra({{Rd = Rs1.sdw<31:0> >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRA
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0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRAX
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}
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0x28: decode RS1 {
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0x0: rdy({{Rd = YValue;}}); //RDY
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0x2: rdccr({{Rd = Ccr;}}); //RDCCR
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0x3: rdasi({{Rd = Asi;}}); //RDASI
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0x4: PrivTick::rdtick({{Rd = Tick;}});
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0x5: rdpc({{Rd = xc->regs.pc;}}); //RDPC
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0x6: rdfprs({{Rd = Fprs;}}); //RDFPRS
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0xF: decode I {
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0x0: Noop::membar({{//Membar isn't needed yet}});
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0x1: Noop::stbar({{//Stbar isn't needed yet}});
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}
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}
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0x2A: decode RS1 {
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format Priv
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{
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0x0: rdprtpc({{
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Rd = xc->readMiscReg(MISCREG_TPC_BASE + tl);
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}});
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0x1: rdprtnpc({{
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Rd = xc->readMiscReg(MISCREG_TNPC_BASE + tl);
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}});
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0x2: rdprtstate({{
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Rd = xc->readMiscReg(MISCREG_TSTATE_BASE + tl);
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}});
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0x3: rdprtt({{
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Rd = xc->readMiscReg(MISCREG_TT_BASE + tl);
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}});
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0x4: rdprtick({{Rd = Tick;}});
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0x5: rdprtba({{Rd = Tba;}});
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0x6: rdprpstate({{Rd = Pstate;}});
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0x7: rdprtl({{Rd = Tl;}});
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0x8: rdprpil({{Rd = Pil;}});
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0x9: rdprcwp({{Rd = Cwp;}});
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0xA: rdprcansave({{Rd = Cansave;}});
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0xB: rdprcanrestore({{Rd = CanRestore;}});
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0xC: rdprcleanwin({{Rd = Cleanwin;}});
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0xD: rdprotherwin({{Rd = Otherwin;}});
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0xE: rdprwstate({{Rd = Wstate;}});
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}
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//The floating point queue isn't implemented right now.
|
|
0xF: Trap::rdprfq({{fault = IllegalInstruction;}});
|
|
0x1F: Priv::rdprver({{Rd = Ver;}});
|
|
}
|
|
0x2B: BasicOperate::flushw({{\\window toilet}}); //FLUSHW
|
|
0x2C: movcc({{
|
|
ccBank = (MOVCC3 << 2) | CC;
|
|
switch(ccBank)
|
|
{
|
|
case 0: case 1: case 2: case 3:
|
|
fault = new FpDisabled;
|
|
break;
|
|
case 5: case 7:
|
|
fault = new IllegalInstruction;
|
|
break;
|
|
case 4:
|
|
if(passesCondition(CcrIcc, COND4))
|
|
Rd = (I ? SIMM11.sdw : RS2);
|
|
break;
|
|
case 6:
|
|
if(passesCondition(CcrXcc, COND4))
|
|
Rd = (I ? SIMM11.sdw : RS2);
|
|
break;
|
|
}
|
|
}});//MOVcc
|
|
0x2D: sdivx({{
|
|
int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
|
if(val2 == 0) fault = new DivisionByZero;
|
|
else Rd.sdw = Rs1.sdw / val2;
|
|
}});//SDIVX
|
|
0x2E: decode RS1 {
|
|
0x0: IntegerOp::popc({{
|
|
int64_t count = 0, val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
|
uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4}
|
|
for(unsigned int x = 0; x < 16; x++)
|
|
{
|
|
count += oneBits[val2 & 0xF];
|
|
val2 >> 4;
|
|
}
|
|
}});//POPC
|
|
}
|
|
0x2F: movr({{
|
|
uint64_t val2 = (I ? SIMM10.sdw : Rs2.sdw);
|
|
switch(RCOND3)
|
|
{
|
|
case 0: case 4:
|
|
fault = IllegalInstruction;
|
|
break;
|
|
case 1:
|
|
if(Rs1 == 0) Rd = val2;
|
|
break;
|
|
case 2:
|
|
if(Rs1 <= 0) Rd = val2;
|
|
break;
|
|
case 3:
|
|
if(Rs1 = 0) Rd = val2;
|
|
break;
|
|
case 5:
|
|
if(Rs1 != 0) Rd = val2;
|
|
break;
|
|
case 6:
|
|
if(Rs1 > 0) Rd = val2;
|
|
break;
|
|
case 7:
|
|
if(Rs1 >= 0) Rd = val2;
|
|
break;
|
|
}
|
|
}});//MOVR
|
|
0x30: decode RD {
|
|
0x0: wry({{
|
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
|
Y = Rs1 ^ val2;
|
|
}});//WRY
|
|
0x2: wrccr({{
|
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
|
Ccr = Rs1 ^ val2;
|
|
}});//WRCCR
|
|
0x3: wrasi({{
|
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
|
Asi = Rs1 ^ val2;
|
|
}});//WRASI
|
|
0x6: wrfprs({{
|
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
|
Asi = Rs1 ^ val2;
|
|
}});//WRFPRS
|
|
0xF: Trap::sir({{fault = new SoftwareInitiatedReset;}});
|
|
}
|
|
0x31: decode FCN {
|
|
0x0: BasicOperate::saved({{\\Boogy Boogy}}); //SAVED
|
|
0x1: BasicOperate::restored({{\\Boogy Boogy}}); //RESTORED
|
|
}
|
|
0x32: decode RD {
|
|
format Priv
|
|
{
|
|
0x0: wrprtpc({{
|
|
xc->setMiscReg(MISCREG_TPC_BASE + tl,
|
|
Rs1 ^ Rs2_or_imm13);
|
|
}});
|
|
0x1: wrprtnpc({{
|
|
xc->setMiscReg(MISCREG_TNPC_BASE + tl,
|
|
Rs1 ^ Rs2_or_imm13);
|
|
}});
|
|
0x2: wrprtstate({{
|
|
xc->setMiscReg(MISCREG_TSTATE_BASE + tl,
|
|
Rs1 ^ Rs2_or_imm13);
|
|
}});
|
|
0x3: wrprtt({{
|
|
xc->setMiscReg(MISCREG_TT_BASE + tl,
|
|
Rs1 ^ Rs2_or_imm13);
|
|
}});
|
|
0x4: wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
|
|
0x5: wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
|
|
0x6: wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
|
|
0x7: wrprtl({{Tl = Rs1 ^ Rs2_or_imm13;}});
|
|
0x8: wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
|
|
0x9: wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
|
|
0xA: wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
|
|
0xB: wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
|
|
0xC: wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
|
|
0xD: wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
|
|
0xE: wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
|
|
}
|
|
}
|
|
|
|
0x34: Trap::fpop1({{fault = new FpDisabled;}});
|
|
0x35: Trap::fpop2({{fault = new FpDisabled;}});
|
|
|
|
|
|
0x38: Branch::jmpl({{//Stuff}}); //JMPL
|
|
0x39: Branch::return({{//Other Stuff}}); //RETURN
|
|
0x3A: decode CC
|
|
{
|
|
0x0: Trap::tcci({{
|
|
#if FULL_SYSTEM
|
|
fault = new TrapInstruction;
|
|
#else
|
|
if(passesCondition(ccr_icc, machInst<25:28>))
|
|
// At least glibc only uses trap 0,
|
|
// solaris/sunos may use others
|
|
assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0);
|
|
xc->syscall();
|
|
#endif
|
|
}});
|
|
0x2: Trap::tccx({{
|
|
#if FULL_SYSTEM
|
|
fault = new TrapInstruction;
|
|
#else
|
|
if(passesCondition(ccr_xcc, machInst<25:28>))
|
|
// At least glibc only uses trap 0,
|
|
// solaris/sunos may use others
|
|
assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0);
|
|
xc->syscall();
|
|
#endif
|
|
}});
|
|
}
|
|
0x3B: BasicOperate::flush({{//Lala}}); //FLUSH
|
|
0x3C: BasicOperate::save({{//leprechauns); //SAVE
|
|
0x3D: BasicOperate::restore({{//Eat my short int}}); //RESTORE
|
|
0x3E: decode FCN {
|
|
0x1: BasicOperate::done({{//Done thing}}); //DONE
|
|
0x2: BasicOperate::retry({{//Retry thing}}); //RETRY
|
|
}
|
|
}
|
|
}
|
|
0x3: decode OP3 {
|
|
format Mem {
|
|
0x00: lduw({{Rd.uw = Mem.uw;}}); //LDUW
|
|
0x01: ldub({{Rd.ub = Mem.ub;}}); //LDUB
|
|
0x02: lduh({{Rd.uhw = Mem.uhw;}}); //LDUH
|
|
0x03: ldd({{
|
|
uint64_t val = Mem.udw;
|
|
setIntReg(RD & (~1), val<31:0>);
|
|
setIntReg(RD | 1, val<63:32>);
|
|
}});//LDD
|
|
0x04: stw({{Mem.sw = Rd.sw;}}); //STW
|
|
0x05: stb({{Mem.sb = Rd.sb;}}); //STB
|
|
0x06: sth({{Mem.shw = Rd.shw;}}); //STH
|
|
0x07: std({{
|
|
Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32);
|
|
}});//STD
|
|
0x08: ldsw({{Rd.sw = Mem.sw;}}); //LDSW
|
|
0x09: ldsb({{Rd.sb = Mem.sb;}}); //LDSB
|
|
0x0A: ldsh({{Rd.shw = Mem.shw;}}); //LDSH
|
|
0x0B: ldx({{Rd.udw = Mem.udw;}}); //LDX
|
|
|
|
0x0D: ldstub({{
|
|
Rd.ub = Mem.ub;
|
|
Mem.ub = 0xFF;
|
|
}}); //LDSTUB
|
|
0x0E: stx({{Rd.udw = Mem.udw;}}); //STX
|
|
0x0F: swap({{
|
|
uint32_t temp = Rd.uw;
|
|
Rd.uw = Mem.uw;
|
|
Mem.uw = temp;
|
|
}}); //SWAP
|
|
0x10: lduwa({{Rd.uw = Mem.uw;}}); //LDUWA
|
|
0x11: lduba({{Rd.ub = Mem.ub;}}); //LDUBA
|
|
0x12: lduha({{Rd.uhw = Mem.uhw;}}); //LDUHA
|
|
0x13: ldda({{
|
|
uint64_t val = Mem.udw;
|
|
setIntReg(RD & (~1), val<31:0>);
|
|
setIntReg(RD | 1, val<63:32>);
|
|
}}); //LDDA
|
|
0x14: stwa({{Mem.uw = Rd.uw;}}); //STWA
|
|
0x15: stba({{Mem.ub = Rd.ub;}}); //STBA
|
|
0x16: stha({{Mem.uhw = Rd.uhw;}}); //STHA
|
|
0x17: stda({{
|
|
Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32);
|
|
}}); //STDA
|
|
0x18: ldswa({{Rd.sw = Mem.sw;}}); //LDSWA
|
|
0x19: ldsba({{Rd.sb = Mem.sb;}}); //LDSBA
|
|
0x1A: ldsha({{Rd.shw = Mem.shw;}}); //LDSHA
|
|
0x1B: ldxa({{Rd.sdw = Mem.sdw;}}); //LDXA
|
|
|
|
0x1D: ldstuba({{
|
|
Rd.ub = Mem.ub;
|
|
Mem.ub = 0xFF;
|
|
}}); //LDSTUBA
|
|
0x1E: stxa({{Mem.sdw = Rd.sdw}}); //STXA
|
|
0x1F: swapa({{
|
|
uint32_t temp = Rd.uw;
|
|
Rd.uw = Mem.uw;
|
|
Mem.uw = temp;
|
|
}}); //SWAPA
|
|
0x20: Trap::ldf({{fault = new FpDisabled;}});
|
|
0x21: decode X {
|
|
0x0: Trap::ldfsr({{fault = new FpDisabled;}});
|
|
0x1: Trap::ldxfsr({{fault = new FpDisabled;}});
|
|
}
|
|
0x22: Trap::ldqf({{fault = new FpDisabled;}});
|
|
0x23: Trap::lddf({{fault = new FpDisabled;}});
|
|
0x24: Trap::stf({{fault = new FpDisabled;}});
|
|
0x25: decode X {
|
|
0x0: Trap::stfsr({{fault = new FpDisabled;}});
|
|
0x1: Trap::stxfsr({{fault = new FpDisabled;}});
|
|
}
|
|
0x26: Trap::stqf({{fault = new FpDisabled;}});
|
|
0x27: Trap::stdf({{fault = new FpDisabled;}});
|
|
|
|
0x2D: Noop::prefetch({{ }}); //PREFETCH
|
|
|
|
0x30: Trap::ldfa({{return new FpDisabled;}});
|
|
|
|
0x32: Trap::ldqfa({{fault = new FpDisabled;}});
|
|
0x33: Trap::lddfa({{fault = new FpDisabled;}});
|
|
0x34: Trap::stfa({{fault = new FpDisabled;}});
|
|
0x35: Trap::stqfa({{fault = new FpDisabled;}});
|
|
0x36: Trap::stdfa({{fault = new FpDisabled;}});
|
|
|
|
0x3C: Cas::casa(
|
|
{{uint64_t val = Mem.uw;
|
|
if(Rs2.uw == val)
|
|
Mem.uw = Rd.uw;
|
|
Rd.uw = val;
|
|
}}); //CASA
|
|
0x3D: Noop::prefetcha({{ }}); //PREFETCHA
|
|
0x3E: Cas::casxa(
|
|
{{uint64_t val = Mem.udw;
|
|
if(Rs2 == val)
|
|
Mem.udw = Rd;
|
|
Rd = val;
|
|
}}); //CASXA
|
|
}
|
|
}
|
|
}
|