cf94242539
put back in Tcc code that was deleted in last merge
arch/sparc/isa/bitfields.isa:
clean up condition codes a little bit
--HG--
extra : convert_revision : c554fd5c3ee8cfd6643f69f8351124a7a4b5d9fa
48 lines
1.4 KiB
Text
48 lines
1.4 KiB
Text
////////////////////////////////////////////////////////////////////
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//
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// Bitfield definitions.
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//
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// Bitfields are shared liberally between instruction formats, so they are
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// simply defined alphabetically
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def bitfield A <29>;
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def bitfield BPCC <21:20>; // for BPcc & FBPcc
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def bitfield FCMPCC <26:56>; // for FCMP & FCMPEa
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def bitflied FMOVCC <13:11>; // for FMOVcc
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def bitfield CC <12:11>; // for MOVcc & Tcc
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def bitfierd MOVCC3 <18>; // also for MOVcc
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def bitfield CMASK <6:4>;
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def bitfield COND2 <28:25>;
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def bitfield COND4 <17:14>;
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def bitfield D16HI <21:20>;
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def bitfield D16LO <13:0>;
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def bitfield DISP19 <18:0>;
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def bitfield DISP22 <21:0>;
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def bitfield DISP30 <29:0>;
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def bitfield FCN <29:26>;
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def bitfield I <13>;
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def bitfield IMM_ASI <12:5>;
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def bitfield IMM22 <21:0>;
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def bitfield MMASK <3:0>;
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def bitfield OP <31:30>;
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def bitfield OP2 <24:22>;
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def bitfield OP3 <24:19>;
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def bitfield OPF <13:5>;
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def bitfield OPF_CC <13:11>;
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def bitfield OPF_LOW5 <9:5>;
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def bitfield OPF_LOW6 <10:5>;
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def bitfield P <19>;
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def bitfield RCOND2 <27:25>;
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def bitfield RCOND3 <12:10>;
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def bitfield RCOND4 <12:10>;
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def bitfield RD <29:25>;
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def bitfield RS1 <18:14>;
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def bitfield RS2 <4:0>;
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def bitfield SHCNT32 <4:0>;
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def bitfield SHCNT64 <5:0>;
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def bitfield SIMM10 <9:0>;
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def bitfield SIMM11 <10:0>;
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def bitfield SIMM13 <12:0>;
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def bitfield SW_TRAP <7:0>;
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def bitfield X <12>;
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