377 lines
43 KiB
Text
377 lines
43 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 1.652607 # Number of seconds simulated
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sim_ticks 1652606827000 # Number of ticks simulated
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final_tick 1652606827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 715148 # Simulator instruction rate (inst/s)
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host_op_rate 1322389 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1429304042 # Simulator tick rate (ticks/s)
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host_mem_usage 236556 # Number of bytes of host memory used
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host_seconds 1156.23 # Real time elapsed on the host
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sim_insts 826877110 # Number of instructions simulated
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sim_ops 1528988700 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 123584 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 27359872 # Number of bytes read from this memory
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system.physmem.bytes_read::total 27483456 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 123584 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 123584 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 20708480 # Number of bytes written to this memory
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system.physmem.bytes_written::total 20708480 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 1931 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 427498 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 429429 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 323570 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 323570 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 74781 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 16555585 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 16630366 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 74781 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 74781 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 12530797 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 12530797 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 12530797 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 74781 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 16555585 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 29161162 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.workload.num_syscalls 551 # Number of system calls
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system.cpu.numCycles 3305213654 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 826877110 # Number of instructions committed
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system.cpu.committedOps 1528988700 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 1528317558 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
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system.cpu.num_func_calls 0 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls
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system.cpu.num_int_insts 1528317558 # number of integer instructions
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system.cpu.num_fp_insts 0 # number of float instructions
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system.cpu.num_int_register_reads 4441632632 # number of times the integer registers were read
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system.cpu.num_int_register_writes 1993077392 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
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system.cpu.num_mem_refs 533262341 # number of memory refs
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system.cpu.num_load_insts 384102156 # Number of load instructions
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system.cpu.num_store_insts 149160185 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 3305213654 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.replacements 1253 # number of replacements
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system.cpu.icache.tagsinuse 881.608211 # Cycle average of tags in use
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system.cpu.icache.total_refs 1068344252 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 379653.252310 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 881.608211 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.430473 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.430473 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 1068344252 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 1068344252 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 1068344252 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 1068344252 # number of overall hits
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system.cpu.icache.overall_hits::total 1068344252 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses
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system.cpu.icache.overall_misses::total 2814 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 120792000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 120792000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 120792000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 120792000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 120792000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 120792000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 1068347066 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 1068347066 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 1068347066 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 1068347066 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 1068347066 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 1068347066 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42925.373134 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total 42925.373134 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 42925.373134 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total 42925.373134 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 42925.373134 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total 42925.373134 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 112350000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 112350000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 112350000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 112350000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 112350000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 112350000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39925.373134 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39925.373134 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39925.373134 # average overall mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::total 39925.373134 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39925.373134 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::total 39925.373134 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 2514362 # number of replacements
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system.cpu.dcache.tagsinuse 4086.432071 # Cycle average of tags in use
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system.cpu.dcache.total_refs 530743928 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 210.741624 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 8218649000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_blocks::cpu.data 4086.432071 # Average occupied blocks per requestor
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system.cpu.dcache.occ_percent::cpu.data 0.997664 # Average percentage of cache occupancy
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system.cpu.dcache.occ_percent::total 0.997664 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 382374771 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 382374771 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 148369157 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 148369157 # number of WriteReq hits
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system.cpu.dcache.demand_hits::cpu.data 530743928 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 530743928 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits::cpu.data 530743928 # number of overall hits
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system.cpu.dcache.overall_hits::total 530743928 # number of overall hits
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system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses
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system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses
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system.cpu.dcache.overall_misses::total 2518458 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::cpu.data 33364275000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_latency::total 33364275000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::cpu.data 19892603500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 19892603500 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::cpu.data 53256878500 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency::total 53256878500 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::cpu.data 53256878500 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency::total 53256878500 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::cpu.data 384102185 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 384102185 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.demand_accesses::cpu.data 533262386 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::total 533262386 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses::cpu.data 533262386 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses::total 533262386 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses
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system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses
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system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses
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system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses
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system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19314.579481 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_miss_latency::total 19314.579481 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25147.278154 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::total 25147.278154 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::cpu.data 21146.621663 # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 21146.621663 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 21146.621663 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::total 21146.621663 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.writebacks::writebacks 2297113 # number of writebacks
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system.cpu.dcache.writebacks::total 2297113 # number of writebacks
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system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses
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system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses
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system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses
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system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28182031000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_latency::total 28182031000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17519463000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 17519463000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45701494000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::total 45701494000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45701494000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::total 45701494000 # number of overall MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses
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system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16314.578323 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16314.578323 # average ReadReq mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22147.267409 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22147.267409 # average WriteReq mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18146.617494 # average overall mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency::total 18146.617494 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18146.617494 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::total 18146.617494 # average overall mshr miss latency
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.replacements 403150 # number of replacements
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system.cpu.l2cache.tagsinuse 29113.385897 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 3572765 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 435501 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 8.203804 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 773011482000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 21035.861795 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 79.696350 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 7997.827752 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.641964 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.002432 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.244074 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.888470 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 883 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1509854 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 1510737 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 2297113 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 2297113 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 581106 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 581106 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 883 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 2090960 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2091843 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 883 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 2090960 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2091843 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 1931 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 217560 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 219491 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 209938 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 209938 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 1931 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 427498 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 429429 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 1931 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 427498 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 429429 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100412000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11313120000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 11413532000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10916779000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 10916779000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 100412000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 22229899000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 22330311000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 100412000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 22229899000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 22330311000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 2814 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1727414 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 1730228 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 2297113 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 2297113 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 791044 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 791044 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 2518458 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2521272 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 2518458 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.686212 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.125945 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.126857 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.265394 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.265394 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.686212 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.169746 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.170322 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.686212 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.169746 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.170322 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.014290 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.014290 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.007018 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 52000.006986 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.007018 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 52000.006986 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 323570 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 323570 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1931 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 217560 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 219491 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 209938 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 209938 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1931 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 427498 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 429429 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1931 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 427498 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 429429 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 77240000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8702400000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8779640000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8397520000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8397520000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 77240000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17099920000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 17177160000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 77240000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17099920000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 17177160000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.686212 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.125945 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.126857 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265394 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265394 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.686212 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.169746 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.170322 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.686212 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.169746 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.170322 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|