269 lines
29 KiB
Text
269 lines
29 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 2210994 # Simulator instruction rate (inst/s)
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host_mem_usage 217324 # Number of bytes of host memory used
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host_seconds 257.37 # Real time elapsed on the host
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host_tick_rate 2806251427 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 569034848 # Number of instructions simulated
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sim_seconds 0.722234 # Number of seconds simulated
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sim_ticks 722234364000 # Number of ticks simulated
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system.cpu.dcache.LoadLockedReq_accesses 1488541 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_hits 1488541 # number of LoadLockedReq hits
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system.cpu.dcache.ReadReq_accesses 123740317 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 19807.762778 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 16807.762778 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 122957659 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 15502704000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.006325 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 782658 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 13154730000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.006325 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 782658 # number of ReadReq MSHR misses
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system.cpu.dcache.StoreCondReq_accesses 1488541 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_hits 1488541 # number of StoreCondReq hits
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system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 28150.625947 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 25150.625947 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 53883046 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 10028942000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.006568 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 356260 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 8960162000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.006568 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 356260 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 157.884753 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 177979623 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 22417.457622 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 176840705 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 25531646000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.006399 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 1138918 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 22114892000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.006399 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 1138918 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.occ_blocks::0 4065.490059 # Average occupied blocks per context
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system.cpu.dcache.occ_percent::0 0.992551 # Average percentage of cache occupancy
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system.cpu.dcache.overall_accesses 177979623 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 22417.457622 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 176840705 # number of overall hits
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system.cpu.dcache.overall_miss_latency 25531646000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.006399 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 1138918 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 22114892000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.006399 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 1138918 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 1134822 # number of replacements
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system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4065.490059 # Cycle average of tags in use
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system.cpu.dcache.total_refs 179817787 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 11889987000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 1025440 # number of writebacks
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.icache.ReadReq_accesses 516611385 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 24743.338252 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 21743.338252 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 516599864 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 285068000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000022 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 11521 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 250505000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 11521 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 44839.845847 # Average number of references to valid blocks.
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 516611385 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 24743.338252 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency
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system.cpu.icache.demand_hits 516599864 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 285068000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000022 # miss rate for demand accesses
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system.cpu.icache.demand_misses 11521 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 250505000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000022 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 11521 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.occ_blocks::0 984.426148 # Average occupied blocks per context
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system.cpu.icache.occ_percent::0 0.480677 # Average percentage of cache occupancy
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system.cpu.icache.overall_accesses 516611385 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 24743.338252 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 516599864 # number of overall hits
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system.cpu.icache.overall_miss_latency 285068000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000022 # miss rate for overall accesses
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system.cpu.icache.overall_misses 11521 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 250505000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000022 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 11521 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 9788 # number of replacements
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system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 984.426148 # Cycle average of tags in use
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system.cpu.icache.total_refs 516599864 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.l2cache.ReadExReq_accesses 356260 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadExReq_hits 236229 # number of ReadExReq hits
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system.cpu.l2cache.ReadExReq_miss_latency 6241612000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_rate 0.336920 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_misses 120031 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 4801240000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.336920 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_mshr_misses 120031 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadReq_accesses 794179 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_hits 683006 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_miss_latency 5780996000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_rate 0.139985 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_misses 111173 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency 4446920000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate 0.139985 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_misses 111173 # number of ReadReq MSHR misses
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system.cpu.l2cache.Writeback_accesses 1025440 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.Writeback_hits 1025440 # number of Writeback hits
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_refs 6.145937 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.demand_accesses 1150439 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.demand_hits 919235 # number of demand (read+write) hits
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system.cpu.l2cache.demand_miss_latency 12022608000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_rate 0.200970 # miss rate for demand accesses
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system.cpu.l2cache.demand_misses 231204 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.demand_mshr_miss_latency 9248160000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_rate 0.200970 # mshr miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_misses 231204 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.occ_blocks::0 5849.157602 # Average occupied blocks per context
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system.cpu.l2cache.occ_blocks::1 14594.006011 # Average occupied blocks per context
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system.cpu.l2cache.occ_percent::0 0.178502 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::1 0.445374 # Average percentage of cache occupancy
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system.cpu.l2cache.overall_accesses 1150439 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_hits 919235 # number of overall hits
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system.cpu.l2cache.overall_miss_latency 12022608000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_rate 0.200970 # miss rate for overall accesses
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system.cpu.l2cache.overall_misses 231204 # number of overall misses
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.l2cache.overall_mshr_miss_latency 9248160000 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_rate 0.200970 # mshr miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_misses 231204 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.l2cache.replacements 212089 # number of replacements
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system.cpu.l2cache.sampled_refs 232128 # Sample count of references to valid blocks.
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.l2cache.tagsinuse 20443.163614 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 1426644 # Total number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 513135223000 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.writebacks 172302 # number of writebacks
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 1444468728 # number of cpu cycles simulated
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.num_busy_cycles 1444468728 # Number of busy cycles
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system.cpu.num_conditional_control_insts 95872736 # number of instructions that are conditional controls
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system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
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system.cpu.num_fp_insts 16 # number of float instructions
|
|
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
|
|
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
|
system.cpu.num_func_calls 15725605 # number of times a function call or return occured
|
|
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
|
system.cpu.num_insts 569034848 # Number of instructions executed
|
|
system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses
|
|
system.cpu.num_int_insts 470727703 # number of integer instructions
|
|
system.cpu.num_int_register_reads 1511252780 # number of times the integer registers were read
|
|
system.cpu.num_int_register_writes 425113002 # number of times the integer registers were written
|
|
system.cpu.num_load_insts 126029556 # Number of load instructions
|
|
system.cpu.num_mem_refs 182890035 # number of memory refs
|
|
system.cpu.num_store_insts 56860479 # Number of store instructions
|
|
system.cpu.workload.num_syscalls 548 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|