ca0fd665dc
Names of DRAM configurations were updated to reflect both
the channel and device data width.
Previous naming format was:
<DEVICE_TYPE>_<DATA_RATE>_<CHANNEL_WIDTH>
The following nomenclature is now used:
<DEVICE_TYPE>_<DATA_RATE>_<n>x<w>
where n = The number of devices per rank on the channel
x = Device width
Total channel width can be calculated by n*w
Example:
A 64-bit DDR4, 2400 channel consisting of 4-bit devices:
n = 16
w = 4
The resulting configuration name is:
DDR4_2400_16x4
Updated scripts to match new naming convention.
Added unique configurations for DDR4 for:
1) 16x4
2) 8x8
3) 4x16
Change-Id: Ibd7f763b7248835c624309143cb9fc29d56a69d1
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
427 lines
19 KiB
Python
427 lines
19 KiB
Python
# Copyright (c) 2012-2013 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2015 The University of Bologna
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Erfan Azarkhish
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# Abdul Mutaal Ahmad
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# A Simplified model of a complete HMC device. Based on:
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# [1] http://www.hybridmemorycube.org/specification-download/
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# [2] High performance AXI-4.0 based interconnect for extensible smart memory
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# cubes(E. Azarkhish et. al)
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# [3] Low-Power Hybrid Memory Cubes With Link Power Management and Two-Level
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# Prefetching (J. Ahn et. al)
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# [4] Memory-centric system interconnect design with Hybrid Memory Cubes
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# (G. Kim et. al)
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# [5] Near Data Processing, Are we there yet? (M. Gokhale)
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# http://www.cs.utah.edu/wondp/gokhale.pdf
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# [6] openHMC - A Configurable Open-Source Hybrid Memory Cube Controller
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# (J. Schmidt)
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# [7] Hybrid Memory Cube performance characterization on data-centric
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# workloads (M. Gokhale)
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#
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# This script builds a complete HMC device composed of vault controllers,
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# serial links, the main internal crossbar, and an external hmc controller.
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#
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# - VAULT CONTROLLERS:
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# Instances of the HMC_2500_1x32 class with their functionality specified in
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# dram_ctrl.cc
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#
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# - THE MAIN XBAR:
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# This component is simply an instance of the NoncoherentXBar class, and its
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# parameters are tuned to [2].
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#
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# - SERIAL LINKS CONTROLLER:
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# SerialLink is a simple variation of the Bridge class, with the ability to
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# account for the latency of packet serialization and controller latency. We
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# assume that the serializer component at the transmitter side does not need
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# to receive the whole packet to start the serialization. But the
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# deserializer waits for the complete packet to check its integrity first.
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#
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# * Bandwidth of the serial links is not modeled in the SerialLink component
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# itself.
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#
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# * Latency of serial link controller is composed of SerDes latency + link
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# controller
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#
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# * It is inferred from the standard [1] and the literature [3] that serial
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# links share the same address range and packets can travel over any of
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# them so a load distribution mechanism is required among them.
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#
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# -----------------------------------------
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# | Host/HMC Controller |
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# | ---------------------- |
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# | | Link Aggregator | opt |
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# | ---------------------- |
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# | ---------------------- |
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# | | Serial Link + Ser | * 4 |
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# | ---------------------- |
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# |---------------------------------------
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# -----------------------------------------
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# | Device
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# | ---------------------- |
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# | | Xbar | * 4 |
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# | ---------------------- |
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# | ---------------------- |
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# | | Vault Controller | * 16 |
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# | ---------------------- |
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# | ---------------------- |
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# | | Memory | |
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# | ---------------------- |
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# |---------------------------------------|
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#
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# In this version we have present 3 different HMC archiecture along with
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# alongwith their corresponding test script.
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#
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# same: It has 4 crossbars in HMC memory. All the crossbars are connected
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# to each other, providing complete memory range. This archicture also covers
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# the added latency for sending a request to non-local vault(bridge in b/t
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# crossbars). All the 4 serial links can access complete memory. So each
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# link can be connected to separate processor.
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#
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# distributed: It has 4 crossbars inside the HMC. Crossbars are not
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# connected.Through each crossbar only local vaults can be accessed. But to
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# support this architecture we need a crossbar between serial links and
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# processor.
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#
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# mixed: This is a hybrid architecture. It has 4 crossbars inside the HMC.
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# 2 Crossbars are connected to only local vaults. From other 2 crossbar, a
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# request can be forwarded to any other vault.
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import optparse
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import m5
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from m5.objects import *
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# A single Hybrid Memory Cube (HMC)
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class HMCSystem(SubSystem):
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#*****************************CROSSBAR PARAMETERS*************************
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# Flit size of the main interconnect [1]
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xbar_width = Param.Unsigned(32, "Data width of the main XBar (Bytes)")
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# Clock frequency of the main interconnect [1]
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# This crossbar, is placed on the logic-based of the HMC and it has its
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# own voltage and clock domains, different from the DRAM dies or from the
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# host.
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xbar_frequency = Param.Frequency('1GHz', "Clock Frequency of the main "
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"XBar")
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# Arbitration latency of the HMC XBar [1]
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xbar_frontend_latency = Param.Cycles(1, "Arbitration latency of the XBar")
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# Latency to forward a packet via the interconnect [1](two levels of FIFOs
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# at the input and output of the inteconnect)
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xbar_forward_latency = Param.Cycles(2, "Forward latency of the XBar")
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# Latency to forward a response via the interconnect [1](two levels of
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# FIFOs at the input and output of the inteconnect)
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xbar_response_latency = Param.Cycles(2, "Response latency of the XBar")
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# number of cross which connects 16 Vaults to serial link[7]
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number_mem_crossbar = Param.Unsigned(4, "Number of crossbar in HMC"
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)
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#*****************************SERIAL LINK PARAMETERS***********************
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# Number of serial links controllers [1]
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num_links_controllers = Param.Unsigned(4, "Number of serial links")
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# Number of packets (not flits) to store at the request side of the serial
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# link. This number should be adjusted to achive required bandwidth
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link_buffer_size_req = Param.Unsigned(10, "Number of packets to buffer "
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"at the request side of the serial link")
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# Number of packets (not flits) to store at the response side of the serial
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# link. This number should be adjusted to achive required bandwidth
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link_buffer_size_rsp = Param.Unsigned(10, "Number of packets to buffer "
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"at the response side of the serial link")
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# Latency of the serial link composed by SER/DES latency (1.6ns [4]) plus
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# the PCB trace latency (3ns Estimated based on [5])
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link_latency = Param.Latency('4.6ns', "Latency of the serial links")
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# Clock frequency of the each serial link(SerDes) [1]
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link_frequency = Param.Frequency('10GHz', "Clock Frequency of the serial"
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"links")
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# Clock frequency of serial link Controller[6]
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# clk_hmc[Mhz]= num_lanes_per_link * lane_speed [Gbits/s] /
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# data_path_width * 10^6
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# clk_hmc[Mhz]= 16 * 10 Gbps / 256 * 10^6 = 625 Mhz
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link_controller_frequency = Param.Frequency('625MHz',
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"Clock Frequency of the link controller")
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# Latency of the serial link controller to process the packets[1][6]
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# (ClockDomain = 625 Mhz )
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# used here for calculations only
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link_ctrl_latency = Param.Cycles(4, "The number of cycles required for the"
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"controller to process the packet")
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# total_ctrl_latency = link_ctrl_latency + link_latency
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# total_ctrl_latency = 4(Cycles) * 1.6 ns + 4.6 ns
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total_ctrl_latency = Param.Latency('11ns', "The latency experienced by"
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"every packet regardless of size of packet")
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# Number of parallel lanes in each serial link [1]
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num_lanes_per_link = Param.Unsigned( 16, "Number of lanes per each link")
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# Number of serial links [1]
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num_serial_links = Param.Unsigned(4, "Number of serial links")
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# speed of each lane of serial link - SerDes serial interface 10 Gb/s
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serial_link_speed = Param.UInt64(10, "Gbs/s speed of each lane of"
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"serial link")
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#*****************************PERFORMANCE MONITORING************************
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# The main monitor behind the HMC Controller
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enable_global_monitor = Param.Bool(False, "The main monitor behind the "
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"HMC Controller")
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# The link performance monitors
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enable_link_monitor = Param.Bool(False, "The link monitors" )
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# link aggregator enable - put a cross between buffers & links
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enable_link_aggr = Param.Bool(False, "The crossbar between port and "
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"Link Controller")
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enable_buff_div = Param.Bool(True, "Memory Range of Buffer is"
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"divided between total range")
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#*****************************HMC ARCHITECTURE ************************
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# Memory chunk for 16 vault - numbers of vault / number of crossbars
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mem_chunk = Param.Unsigned(4, "Chunk of memory range for each cross bar "
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"in arch 0")
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# size of req buffer within crossbar, used for modelling extra latency
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# when the reuqest go to non-local vault
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xbar_buffer_size_req = Param.Unsigned(10, "Number of packets to buffer "
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"at the request side of the crossbar")
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# size of response buffer within crossbar, used for modelling extra latency
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# when the response received from non-local vault
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xbar_buffer_size_resp = Param.Unsigned(10, "Number of packets to buffer "
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"at the response side of the crossbar")
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# configure host system with Serial Links
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def config_host_hmc(options, system):
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system.hmc_host=HMCSystem()
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try:
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system.hmc_host.enable_global_monitor = options.enable_global_monitor
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except:
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pass;
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try:
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system.hmc_host.enable_link_monitor = options.enable_link_monitor
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except:
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pass;
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# Serial link Controller with 16 SerDes links at 10 Gbps
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# with serial link ranges w.r.t to architecture
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system.hmc_host.seriallink = [SerialLink(ranges = options.ser_ranges[i],
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req_size=system.hmc_host.link_buffer_size_req,
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resp_size=system.hmc_host.link_buffer_size_rsp,
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num_lanes=system.hmc_host.num_lanes_per_link,
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link_speed=system.hmc_host.serial_link_speed,
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delay=system.hmc_host.total_ctrl_latency)
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for i in xrange(system.hmc_host.num_serial_links)]
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# enable global monitor
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if system.hmc_host.enable_global_monitor:
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system.hmc_host.lmonitor = [ CommMonitor()
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for i in xrange(system.hmc_host.num_serial_links)]
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# set the clock frequency for serial link
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for i in xrange(system.hmc_host.num_serial_links):
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system.hmc_host.seriallink[i].clk_domain = SrcClockDomain(clock=system.
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hmc_host.link_controller_frequency, voltage_domain=
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VoltageDomain(voltage = '1V'))
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# Connect membus/traffic gen to Serial Link Controller for differrent HMC
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# architectures
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if options.arch == "distributed":
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for i in xrange(system.hmc_host.num_links_controllers):
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if system.hmc_host.enable_global_monitor:
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system.membus.master = system.hmc_host.lmonitor[i].slave
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system.hmc_host.lmonitor[i].master = \
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system.hmc_host.seriallink[i].slave
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else:
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system.membus.master = system.hmc_host.seriallink[i].slave
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if options.arch == "mixed":
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if system.hmc_host.enable_global_monitor:
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system.membus.master = system.hmc_host.lmonitor[0].slave
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system.hmc_host.lmonitor[0].master = \
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system.hmc_host.seriallink[0].slave
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system.membus.master = system.hmc_host.lmonitor[1].slave
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system.hmc_host.lmonitor[1].master = \
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system.hmc_host.seriallink[1].slave
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system.tgen[2].port = system.hmc_host.lmonitor[2].slave
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system.hmc_host.lmonitor[2].master = \
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system.hmc_host.seriallink[2].slave
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system.tgen[3].port = system.hmc_host.lmonitor[3].slave
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system.hmc_host.lmonitor[3].master = \
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system.hmc_host.seriallink[3].slave
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else:
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system.membus.master = system.hmc_host.seriallink[0].slave
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system.membus.master = system.hmc_host.seriallink[1].slave
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system.tgen[2].port = system.hmc_host.seriallink[2].slave
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system.tgen[3].port = system.hmc_host.seriallink[3].slave
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if options.arch == "same" :
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for i in xrange(system.hmc_host.num_links_controllers):
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if system.hmc_host.enable_global_monitor:
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system.tgen[i].port = system.hmc_host.lmonitor[i].slave
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system.hmc_host.lmonitor[i].master = \
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system.hmc_host.seriallink[i].slave
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else:
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system.tgen[i].port = system.hmc_host.seriallink[i].slave
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return system
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# Create an HMC device and attach it to the current system
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def config_hmc(options, system, hmc_host):
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# Create HMC device
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system.hmc_dev = HMCSystem()
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# Global monitor
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try:
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system.hmc_dev.enable_global_monitor = options.enable_global_monitor
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except:
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pass;
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try:
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system.hmc_dev.enable_link_monitor = options.enable_link_monitor
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except:
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pass;
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if system.hmc_dev.enable_link_monitor:
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system.hmc_dev.lmonitor = [ CommMonitor()
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for i in xrange(system.hmc_dev.num_links_controllers)]
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# 4 HMC Crossbars located in its logic-base (LoB)
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system.hmc_dev.xbar = [ NoncoherentXBar(width=system.hmc_dev.xbar_width,
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frontend_latency=system.hmc_dev.xbar_frontend_latency,
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forward_latency=system.hmc_dev.xbar_forward_latency,
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response_latency=system.hmc_dev.xbar_response_latency )
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for i in xrange(system.hmc_host.number_mem_crossbar)]
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for i in xrange(system.hmc_dev.number_mem_crossbar):
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system.hmc_dev.xbar[i].clk_domain = SrcClockDomain(
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clock=system.hmc_dev.xbar_frequency,voltage_domain=
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VoltageDomain(voltage='1V'))
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# Attach 4 serial link to 4 crossbar/s
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for i in xrange(system.hmc_dev.num_serial_links):
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if system.hmc_dev.enable_link_monitor:
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system.hmc_host.seriallink[i].master = \
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system.hmc_dev.lmonitor[i].slave
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system.hmc_dev.lmonitor[i].master = system.hmc_dev.xbar[i].slave
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else:
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system.hmc_host.seriallink[i].master = system.hmc_dev.xbar[i].slave
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# Connecting xbar with each other for request arriving at the wrong xbar,
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# then it will be forward to correct xbar. Bridge is used to connect xbars
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if options.arch == "same":
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numx = len(system.hmc_dev.xbar)
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# create a list of buffers
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system.hmc_dev.buffers = [ Bridge(
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req_size=system.hmc_dev.xbar_buffer_size_req,
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resp_size=system.hmc_dev.xbar_buffer_size_resp)
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for i in xrange(numx * (system.hmc_dev.mem_chunk - 1))]
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# Buffer iterator
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it = iter(range(len(system.hmc_dev.buffers)))
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# necesarry to add system_port to one of the xbar
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system.system_port = system.hmc_dev.xbar[3].slave
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# iterate over all the crossbars and connect them as required
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for i in range(numx):
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for j in range(numx):
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# connect xbar to all other xbars except itself
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if i != j:
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# get the next index of buffer
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index = it.next()
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# Change the default values for ranges of bridge
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system.hmc_dev.buffers[index].ranges = system.mem_ranges[
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j * int(system.hmc_dev.mem_chunk):
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(j + 1) * int(system.hmc_dev.mem_chunk)]
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# Connect the bridge between corssbars
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system.hmc_dev.xbar[i].master = system.hmc_dev.buffers[
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index].slave
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system.hmc_dev.buffers[
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index].master = system.hmc_dev.xbar[j].slave
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else:
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# Don't connect the xbar to itself
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pass
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# Two crossbars are connected to all other crossbars-Other 2 vault
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# can only direct traffic to it local vaults
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if options.arch == "mixed":
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system.hmc_dev.buffer30 = Bridge(ranges=system.mem_ranges[0:4])
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system.hmc_dev.xbar[3].master = system.hmc_dev.buffer30.slave
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system.hmc_dev.buffer30.master = system.hmc_dev.xbar[0].slave
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system.hmc_dev.buffer31 = Bridge(ranges=system.mem_ranges[4:8])
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system.hmc_dev.xbar[3].master = system.hmc_dev.buffer31.slave
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system.hmc_dev.buffer31.master = system.hmc_dev.xbar[1].slave
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system.hmc_dev.buffer32 = Bridge(ranges=system.mem_ranges[8:12])
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system.hmc_dev.xbar[3].master = system.hmc_dev.buffer32.slave
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system.hmc_dev.buffer32.master = system.hmc_dev.xbar[2].slave
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system.hmc_dev.buffer20 = Bridge(ranges=system.mem_ranges[0:4])
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system.hmc_dev.xbar[2].master = system.hmc_dev.buffer20.slave
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system.hmc_dev.buffer20.master = system.hmc_dev.xbar[0].slave
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system.hmc_dev.buffer21 = Bridge(ranges=system.mem_ranges[4:8])
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system.hmc_dev.xbar[2].master = system.hmc_dev.buffer21.slave
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system.hmc_dev.buffer21.master = system.hmc_dev.xbar[1].slave
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system.hmc_dev.buffer23 = Bridge(ranges=system.mem_ranges[12:16])
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system.hmc_dev.xbar[2].master = system.hmc_dev.buffer23.slave
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system.hmc_dev.buffer23.master = system.hmc_dev.xbar[3].slave
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