Sophiane Senni ce2722cdd9 mem: Split the hit_latency into tag_latency and data_latency ... If the cache access mode is parallel, i.e. "sequential_access" parameter is set to "False", tags and data are accessed in parallel. Therefore, the hit_latency is the maximum latency between tag_latency and data_latency. On the other hand, if the cache access mode is sequential, i.e. "sequential_access" parameter is set to "True", tags and data are accessed sequentially. Therefore, the hit_latency is the sum of tag_latency plus data_latency. Signed-off-by: Jason Lowe-Power <jason@lowepower.com>		2016-11-30 17:10:27 -05:00
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arch	x86: fix issue with casting in Cvtf2i	2016-11-21 15:35:56 -05:00
base	stats: Add more information to uninitialized error	2016-10-14 09:02:03 -05:00
cpu	cpu: Remove branch predictor function predictInOrder	2016-11-30 17:10:27 -05:00
dev	dev: Fix buffer length when unserializing an eth pkt	2016-11-29 13:04:45 -05:00
doc	sim: Adding support for power models	2016-06-06 17:16:44 +01:00
doxygen	MEM: Put memory system document into doxygen	2012-09-25 11:49:41 -05:00
gpu-compute	gpu-compute: fix segfault when constructing GPUExecContext	2016-11-21 15:40:03 -05:00
kern	alpha: Remove ALPHA tru64 support and associated tests	2016-11-17 04:54:14 -05:00
mem	mem: Split the hit_latency into tag_latency and data_latency	2016-11-30 17:10:27 -05:00
proto	cpu: Support virtual addr in elastic traces	2015-12-07 16:42:16 -06:00
python	base: eliminate ipython warning	2016-09-15 18:21:38 +01:00
sim	alpha: Remove ALPHA tru64 support and associated tests	2016-11-17 04:54:14 -05:00
unittest	style: remove trailing whitespace	2016-02-06 17:21:18 -08:00
Doxyfile	Doxygen: Update the version of the Doxyfile	2012-10-11 06:38:42 -04:00
SConscript	scons: fix sanitizer flags with multiple sanitizers	2016-11-28 12:44:54 -05:00