sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
gem5/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
Andreas Hansson c4e91289ae stats: Bump stats for filter, crossbar and config changes 
This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
2014-09-20 17:18:53 -04:00

917 lines
104 KiB
Text
Raw Blame History

---------- Begin Simulation Statistics ----------
sim_seconds 0.000026 # Number of seconds simulated
sim_ticks 25944000 # Number of ticks simulated
final_tick 25944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 79125 # Simulator instruction rate (inst/s)
host_op_rate 79119 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 142180718 # Simulator tick rate (ticks/s)
host_mem_usage 289004 # Number of bytes of host memory used
host_seconds 0.18 # Real time elapsed on the host
sim_insts 14436 # Number of instructions simulated
sim_ops 14436 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 22016 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9472 # Number of bytes read from this memory
system.physmem.bytes_read::total 31488 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 22016 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 22016 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 344 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 148 # Number of read requests responded to by this memory
system.physmem.num_reads::total 492 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 848596978 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 365094049 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1213691027 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 848596978 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 848596978 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 848596978 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 365094049 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1213691027 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 492 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 492 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 31488 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 31488 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 107 # Per bank write bursts
system.physmem.perBankRdBursts::1 28 # Per bank write bursts
system.physmem.perBankRdBursts::2 51 # Per bank write bursts
system.physmem.perBankRdBursts::3 24 # Per bank write bursts
system.physmem.perBankRdBursts::4 20 # Per bank write bursts
system.physmem.perBankRdBursts::5 0 # Per bank write bursts
system.physmem.perBankRdBursts::6 32 # Per bank write bursts
system.physmem.perBankRdBursts::7 35 # Per bank write bursts
system.physmem.perBankRdBursts::8 4 # Per bank write bursts
system.physmem.perBankRdBursts::9 2 # Per bank write bursts
system.physmem.perBankRdBursts::10 1 # Per bank write bursts
system.physmem.perBankRdBursts::11 0 # Per bank write bursts
system.physmem.perBankRdBursts::12 57 # Per bank write bursts
system.physmem.perBankRdBursts::13 31 # Per bank write bursts
system.physmem.perBankRdBursts::14 61 # Per bank write bursts
system.physmem.perBankRdBursts::15 39 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 25892500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 492 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 288 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 72 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 404.444444 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 264.526762 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 350.678412 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 12 16.67% 16.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 24 33.33% 50.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 7 9.72% 59.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 4 5.56% 65.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 4 5.56% 70.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 3 4.17% 75.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 6 8.33% 83.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1 1.39% 84.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 11 15.28% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 72 # Bytes accessed per row activation
system.physmem.totQLat 2786000 # Total ticks spent queuing
system.physmem.totMemAccLat 12011000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2460000 # Total ticks spent in databus transfers
system.physmem.avgQLat 5662.60 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 24412.60 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1213.69 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1213.69 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 9.48 # Data bus utilization in percentage
system.physmem.busUtilRead 9.48 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.52 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 411 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.54 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 52627.03 # Average gap between requests
system.physmem.pageHitRate 83.54 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 279250 # Time in different power states
system.physmem.memoryStateTime::REF 780000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 22761250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.membus.trans_dist::ReadReq 409 # Transaction distribution
system.membus.trans_dist::ReadResp 408 # Transaction distribution
system.membus.trans_dist::ReadExReq 83 # Transaction distribution
system.membus.trans_dist::ReadExResp 83 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 983 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 983 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31424 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 31424 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 492 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 492 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 492 # Request fanout histogram
system.membus.reqLayer0.occupancy 611000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.4 # Layer utilization (%)
system.membus.respLayer1.occupancy 4586750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 17.7 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.branchPred.lookups 8578 # Number of BP lookups
system.cpu.branchPred.condPredicted 5479 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1058 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 6011 # Number of BTB lookups
system.cpu.branchPred.BTBHits 3046 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 50.673765 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 607 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 51889 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 14152 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 40300 # Number of instructions fetch has processed
system.cpu.fetch.Branches 8578 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 3653 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 16187 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2310 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1000 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 6453 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 567 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 32510 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.239619 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.385650 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 20972 64.51% 64.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 5490 16.89% 81.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 661 2.03% 83.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 508 1.56% 84.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 826 2.54% 87.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 909 2.80% 90.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 334 1.03% 91.36% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 369 1.14% 92.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 2441 7.51% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 32510 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.165314 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.776658 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 11331 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 12526 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 6844 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 654 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1155 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 30561 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 1155 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 11931 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 1436 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 10087 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 6918 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 983 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 27740 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
system.cpu.rename.SQFullEvents 585 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 25096 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 51799 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 42923 # Number of integer rename lookups
system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 11277 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 768 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 786 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 3783 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 3676 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 2348 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 23657 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 726 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 21921 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 57 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 9156 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 6522 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 251 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 32510 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.674285 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.426342 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 24124 74.20% 74.20% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 3065 9.43% 83.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 1561 4.80% 88.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 1482 4.56% 92.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 945 2.91% 95.90% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 726 2.23% 98.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 412 1.27% 99.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 154 0.47% 99.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 41 0.13% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 32510 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 112 49.56% 49.56% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 49.56% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 49.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 49.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 49.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 49.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 49.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 49.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 49.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 49.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 49.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 49.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 49.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 49.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 49.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 49.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 49.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 49.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 49.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 49.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 49.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 49.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 49.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 49.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 49.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 49.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 49.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 49.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 49.56% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 49 21.68% 71.24% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 65 28.76% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 16292 74.32% 74.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.32% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 3506 15.99% 90.32% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 2123 9.68% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 21921 # Type of FU issued
system.cpu.iq.rate 0.422459 # Inst issue rate
system.cpu.iq.fu_busy_cnt 226 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.010310 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 76635 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 33566 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 20237 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 22147 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 34 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1451 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 900 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1155 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1122 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 322 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 25510 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 207 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 3676 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 2348 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 726 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 318 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 259 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 934 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1193 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 20909 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 3349 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 1127 # number of nop insts executed
system.cpu.iew.exec_refs 5373 # number of memory reference insts executed
system.cpu.iew.exec_branches 4425 # Number of branches executed
system.cpu.iew.exec_stores 2024 # Number of stores executed
system.cpu.iew.exec_rate 0.402956 # Inst execution rate
system.cpu.iew.wb_sent 20494 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 20237 # cumulative count of insts written-back
system.cpu.iew.wb_producers 9846 # num instructions producing a value
system.cpu.iew.wb_consumers 12767 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.390006 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.771207 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 10297 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1058 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 30446 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.497996 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.310786 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 23926 78.59% 78.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 3430 11.27% 89.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 1163 3.82% 93.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 612 2.01% 95.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 344 1.13% 96.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 240 0.79% 97.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 396 1.30% 98.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 62 0.20% 99.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 273 0.90% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 30446 # Number of insts commited each cycle
system.cpu.commit.committedInsts 15162 # Number of instructions committed
system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 3673 # Number of memory references committed
system.cpu.commit.loads 2225 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 3358 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 12174 # Number of committed integer instructions.
system.cpu.commit.function_calls 187 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 726 4.79% 4.79% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 10763 70.99% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 2225 14.67% 90.45% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 15162 # Class of committed instruction
system.cpu.commit.bw_lim_events 273 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 54809 # The number of ROB reads
system.cpu.rob.rob_writes 52996 # The number of ROB writes
system.cpu.timesIdled 204 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 19379 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 14436 # Number of Instructions Simulated
system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 3.594417 # CPI: Cycles Per Instruction
system.cpu.cpi_total 3.594417 # CPI: Total CPI of All Threads
system.cpu.ipc 0.278209 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.278209 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 33400 # number of integer regfile reads
system.cpu.int_regfile_writes 18599 # number of integer regfile writes
system.cpu.misc_regfile_reads 7136 # number of misc regfile reads
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
system.cpu.toL2Bus.trans_dist::ReadReq 411 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 692 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 295 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 987 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22144 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 31552 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 494 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 494 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 494 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 247000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 579250 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 233000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 192.510962 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 5925 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 346 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 17.124277 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 192.510962 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.093999 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.093999 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 346 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 253 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.168945 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 13252 # Number of tag accesses
system.cpu.icache.tags.data_accesses 13252 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 5925 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 5925 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 5925 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 5925 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 5925 # number of overall hits
system.cpu.icache.overall_hits::total 5925 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 528 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 528 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 528 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 528 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 528 # number of overall misses
system.cpu.icache.overall_misses::total 528 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 32445000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 32445000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 32445000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 32445000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 32445000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 32445000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 6453 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 6453 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 6453 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 6453 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 6453 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 6453 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081822 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.081822 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.081822 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.081822 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.081822 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.081822 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61448.863636 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 61448.863636 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61448.863636 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 61448.863636 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61448.863636 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 61448.863636 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 42 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 42 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 182 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 182 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 182 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 182 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 182 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 346 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 346 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 346 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 346 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 346 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 346 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23039750 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 23039750 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23039750 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 23039750 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23039750 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 23039750 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.053618 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.053618 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.053618 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66588.872832 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66588.872832 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66588.872832 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 66588.872832 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66588.872832 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 66588.872832 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 226.536653 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 408 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.004902 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 191.902825 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 34.633828 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005856 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001057 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.006913 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012451 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4443 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4443 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 344 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 65 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 409 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 344 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 148 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 492 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses
system.cpu.l2cache.overall_misses::total 492 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22673250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4676500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 27349750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6151000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6151000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 22673250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 10827500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 33500750 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 22673250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 10827500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 33500750 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 346 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 65 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 411 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 346 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 494 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 346 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 494 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994220 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.995134 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994220 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.995951 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994220 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.995951 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65910.610465 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71946.153846 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 66869.804401 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74108.433735 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74108.433735 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65910.610465 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73158.783784 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 68090.955285 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65910.610465 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73158.783784 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 68090.955285 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 409 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 492 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 492 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18347250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3889500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22236750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5131500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5131500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18347250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9021000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 27368250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18347250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9021000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 27368250 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995134 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.995951 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995951 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53335.029070 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59838.461538 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54368.581907 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61825.301205 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61825.301205 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53335.029070 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60952.702703 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53335.029070 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60952.702703 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 98.823294 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 4124 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 28.054422 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 98.823294 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.024127 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.024127 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 9491 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 9491 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 3085 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 3085 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 4118 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 4118 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 4118 # number of overall hits
system.cpu.dcache.overall_hits::total 4118 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 139 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 139 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 548 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 548 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 548 # number of overall misses
system.cpu.dcache.overall_misses::total 548 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8670750 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 8670750 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 26093224 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 26093224 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 34763974 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 34763974 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 34763974 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 34763974 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 3224 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 3224 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 4666 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 4666 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 4666 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 4666 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.043114 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.043114 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.117445 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.117445 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.117445 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.117445 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62379.496403 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 62379.496403 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63797.613692 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 63797.613692 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 63437.908759 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 63437.908759 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 955 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.833333 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 400 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 400 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 400 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 400 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4741000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4741000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6235500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6235500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10976500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 10976500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10976500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 10976500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020161 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020161 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.031719 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.031719 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72938.461538 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72938.461538 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75126.506024 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75126.506024 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
Reference in a new issue View git blame Copy permalink