c4e91289ae
This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
1109 lines
126 KiB
Text
1109 lines
126 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.084956 # Number of seconds simulated
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sim_ticks 84955935500 # Number of ticks simulated
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final_tick 84955935500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 135379 # Simulator instruction rate (inst/s)
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host_op_rate 142711 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 66749907 # Simulator tick rate (ticks/s)
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host_mem_usage 309000 # Number of bytes of host memory used
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host_seconds 1272.75 # Real time elapsed on the host
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sim_insts 172303021 # Number of instructions simulated
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sim_ops 181635953 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 18240 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 35328 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.l2cache.prefetcher 268480 # Number of bytes read from this memory
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system.physmem.bytes_read::total 322048 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 18240 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 18240 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 285 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 552 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.l2cache.prefetcher 4195 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 5032 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 214700 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 415839 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.l2cache.prefetcher 3160227 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 3790765 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 214700 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 214700 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 214700 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 415839 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.l2cache.prefetcher 3160227 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 3790765 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 5032 # Number of read requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.readBursts 5032 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 322048 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 322048 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 395 # Per bank write bursts
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system.physmem.perBankRdBursts::1 288 # Per bank write bursts
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system.physmem.perBankRdBursts::2 188 # Per bank write bursts
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system.physmem.perBankRdBursts::3 388 # Per bank write bursts
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system.physmem.perBankRdBursts::4 399 # Per bank write bursts
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system.physmem.perBankRdBursts::5 367 # Per bank write bursts
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system.physmem.perBankRdBursts::6 381 # Per bank write bursts
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system.physmem.perBankRdBursts::7 279 # Per bank write bursts
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system.physmem.perBankRdBursts::8 314 # Per bank write bursts
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system.physmem.perBankRdBursts::9 341 # Per bank write bursts
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system.physmem.perBankRdBursts::10 369 # Per bank write bursts
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system.physmem.perBankRdBursts::11 260 # Per bank write bursts
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system.physmem.perBankRdBursts::12 244 # Per bank write bursts
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system.physmem.perBankRdBursts::13 279 # Per bank write bursts
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system.physmem.perBankRdBursts::14 295 # Per bank write bursts
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system.physmem.perBankRdBursts::15 245 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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system.physmem.perBankWrBursts::3 0 # Per bank write bursts
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system.physmem.perBankWrBursts::4 0 # Per bank write bursts
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system.physmem.perBankWrBursts::5 0 # Per bank write bursts
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system.physmem.perBankWrBursts::6 0 # Per bank write bursts
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system.physmem.perBankWrBursts::7 0 # Per bank write bursts
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system.physmem.perBankWrBursts::8 0 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 0 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 0 # Per bank write bursts
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system.physmem.perBankWrBursts::13 0 # Per bank write bursts
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system.physmem.perBankWrBursts::14 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 84955621000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 5032 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 1408 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 968 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 484 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 397 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 338 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 315 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 293 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 271 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 257 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 115 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 65 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 62 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 23 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 17 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 13 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 6 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 689 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 467.413643 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 304.114713 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 362.347713 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 143 20.75% 20.75% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 123 17.85% 38.61% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 63 9.14% 47.75% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 69 10.01% 57.76% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 45 6.53% 64.30% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 51 7.40% 71.70% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 42 6.10% 77.79% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 21 3.05% 80.84% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 132 19.16% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 689 # Bytes accessed per row activation
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system.physmem.totQLat 114920157 # Total ticks spent queuing
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system.physmem.totMemAccLat 209270157 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 25160000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 22837.87 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 41587.87 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 3.79 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 3.79 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 0.03 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.97 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
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system.physmem.readRowHits 4343 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 86.31 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 16883072.54 # Average gap between requests
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system.physmem.pageHitRate 86.31 # Row buffer hit rate, read and write combined
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system.physmem.memoryStateTime::IDLE 81214099250 # Time in different power states
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system.physmem.memoryStateTime::REF 2836600000 # Time in different power states
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system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem.memoryStateTime::ACT 905088250 # Time in different power states
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system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.membus.trans_dist::ReadReq 4821 # Transaction distribution
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system.membus.trans_dist::ReadResp 4821 # Transaction distribution
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system.membus.trans_dist::ReadExReq 211 # Transaction distribution
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system.membus.trans_dist::ReadExResp 211 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10064 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 10064 # Packet count per connected master and slave (bytes)
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system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 322048 # Cumulative packet size per connected master and slave (bytes)
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system.membus.pkt_size::total 322048 # Cumulative packet size per connected master and slave (bytes)
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system.membus.snoops 0 # Total snoops (count)
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system.membus.snoop_fanout::samples 5032 # Request fanout histogram
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system.membus.snoop_fanout::mean 0 # Request fanout histogram
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system.membus.snoop_fanout::stdev 0 # Request fanout histogram
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system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
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system.membus.snoop_fanout::0 5032 100.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::min_value 0 # Request fanout histogram
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system.membus.snoop_fanout::max_value 0 # Request fanout histogram
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system.membus.snoop_fanout::total 5032 # Request fanout histogram
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system.membus.reqLayer0.occupancy 5681641 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
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system.membus.respLayer1.occupancy 46027985 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.branchPred.lookups 85925623 # Number of BP lookups
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system.cpu.branchPred.condPredicted 68405598 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 6015157 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 40113883 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 39024614 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 97.284559 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 3701789 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 81904 # Number of incorrect RAS predictions.
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system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 400 # Number of system calls
|
|
system.cpu.numCycles 169911872 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 5595281 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 349266175 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 85925623 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 42726403 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 158254745 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 12044332 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.MiscStallCycles 129 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingQuiesceStallCycles 37 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 592 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 78952832 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 17522 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 169872950 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 2.151005 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 1.046766 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 17324644 10.20% 10.20% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 30203623 17.78% 27.98% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 31840188 18.74% 46.72% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 90504495 53.28% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 169872950 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.505707 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 2.055573 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 17551129 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 17096204 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 122646615 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 6731659 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 5847343 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 11137012 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 190128 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 306601093 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 27639828 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 5847343 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 37738327 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 8403981 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 578579 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 108919553 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 8385167 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 278647204 # Number of instructions processed by rename
|
|
system.cpu.rename.SquashedInsts 13415116 # Number of squashed instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 3048397 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 841923 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 2187656 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 31854 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.FullRegisterEvents 78402 # Number of times there has been no free registers
|
|
system.cpu.rename.RenamedOperands 483062515 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 1196895890 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 297562467 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 3006395 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 190085586 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 23528 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 23420 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 13351603 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 34138378 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 14478835 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 2550837 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 1806189 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 264810642 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 45850 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 214907655 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 5190996 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 82629036 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 219889900 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 634 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 169872950 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.265108 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.017484 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 52803027 31.08% 31.08% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 36096104 21.25% 52.33% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 65778237 38.72% 91.05% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 13576092 7.99% 99.05% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 1571163 0.92% 99.97% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 47813 0.03% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 514 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 169872950 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 35609099 66.11% 66.11% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 152890 0.28% 66.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 66.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 66.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 66.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 66.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.39% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 1075 0.00% 66.40% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.40% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 35725 0.07% 66.46% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 330 0.00% 66.46% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.46% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 815 0.00% 66.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 34388 0.06% 66.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 217 0.00% 66.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 14076935 26.13% 92.66% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 3950981 7.34% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 167347451 77.87% 77.87% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 918969 0.43% 78.30% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.30% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.30% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.30% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.30% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.30% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.30% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.30% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.30% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.30% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.30% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.30% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.30% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.30% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.30% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.30% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.30% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.30% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.30% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 33024 0.02% 78.31% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.31% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 165192 0.08% 78.39% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 245769 0.11% 78.50% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 460683 0.21% 78.75% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 206710 0.10% 78.85% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 71622 0.03% 78.88% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.88% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 32005523 14.89% 93.78% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 13376375 6.22% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 214907655 # Type of FU issued
|
|
system.cpu.iq.rate 1.264818 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 53862656 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.250632 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 654786826 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 345480396 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 204601887 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 3955086 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 2012108 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 1806636 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 266634716 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 2135595 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 1601086 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 6242234 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 7548 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 7115 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 1834201 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 25938 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 647 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 5847343 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 5682283 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 37485 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 264872462 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 34138378 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 14478835 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 23442 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 3828 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 30448 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 7115 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 3233466 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 3245683 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 6479149 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 207525838 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 30720478 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 7381817 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 15970 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 43862877 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 44936358 # Number of branches executed
|
|
system.cpu.iew.exec_stores 13142399 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.221373 # Inst execution rate
|
|
system.cpu.iew.wb_sent 206743657 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 206408523 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 129467920 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 221670950 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.214798 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.584055 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 69532618 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 5840334 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 158431709 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.146553 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.646732 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 73650115 46.49% 46.49% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 41279051 26.05% 72.54% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 22553954 14.24% 86.78% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 9627262 6.08% 92.85% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 3547678 2.24% 95.09% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 2148088 1.36% 96.45% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 1282361 0.81% 97.26% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 989322 0.62% 97.88% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 3353878 2.12% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 158431709 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 172317409 # Number of instructions committed
|
|
system.cpu.commit.committedOps 181650341 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 40540778 # Number of memory references committed
|
|
system.cpu.commit.loads 27896144 # Number of loads committed
|
|
system.cpu.commit.membars 22408 # Number of memory barriers committed
|
|
system.cpu.commit.branches 40300311 # Number of branches committed
|
|
system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 143085667 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 1848934 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 138987812 76.51% 76.51% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 32754 0.02% 77.03% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 77.03% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 154829 0.09% 77.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 238880 0.13% 77.25% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 76016 0.04% 77.29% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 181650341 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 3353878 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 406255589 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 513821131 # The number of ROB writes
|
|
system.cpu.timesIdled 2630 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 38922 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 172303021 # Number of Instructions Simulated
|
|
system.cpu.committedOps 181635953 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 0.986122 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.986122 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.014073 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.014073 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 218958563 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 114511116 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 2904510 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 2441819 # number of floating regfile writes
|
|
system.cpu.cc_regfile_reads 709580018 # number of cc regfile reads
|
|
system.cpu.cc_regfile_writes 229533397 # number of cc regfile writes
|
|
system.cpu.misc_regfile_reads 59318521 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 820036 # number of misc regfile writes
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 119664 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 119664 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 64873 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::HardPFReq 7801 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 8632 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 8632 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 109774 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 211691 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 321465 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3512768 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8850048 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 12362816 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 7801 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 200978 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 5.038815 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.193155 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::5 193177 96.12% 96.12% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::6 7801 3.88% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 200978 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 161464494 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 82370974 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 110177995 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.icache.tags.replacements 54375 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 510.661166 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 78896017 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 54887 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 1437.426294 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 84218922500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 510.661166 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.997385 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.997385 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 251 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 48 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 157960533 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 157960533 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 78896017 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 78896017 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 78896017 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 78896017 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 78896017 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 78896017 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 56806 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 56806 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 56806 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 56806 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 56806 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 56806 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 474677200 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 474677200 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 474677200 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 474677200 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 474677200 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 474677200 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 78952823 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 78952823 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 78952823 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 78952823 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 78952823 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 78952823 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000719 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000719 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000719 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000719 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000719 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000719 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8356.110270 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 8356.110270 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 8356.110270 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 8356.110270 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 8356.110270 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 8356.110270 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 16306 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 2267 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 7.192766 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1919 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 1919 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 1919 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 1919 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 1919 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 1919 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54887 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 54887 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 54887 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 54887 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 54887 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 54887 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 380604754 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 380604754 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 380604754 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 380604754 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 380604754 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 380604754 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000695 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000695 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000695 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6934.333339 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6934.333339 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6934.333339 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 6934.333339 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6934.333339 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 6934.333339 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 435044 # number of hwpf identified
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 3068 # number of hwpf that were already in mshr
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 422406 # number of hwpf that were already in the cache
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 3291 # number of hwpf that were already in the prefetch queue
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 894 # number of hwpf removed because MSHR allocated
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 5385 # number of hwpf issued
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 26500 # number of hwpf spanning a virtual page
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 3680.652694 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 181097 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 4769 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 37.973789 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 700.245747 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 217.753448 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 276.465568 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2486.187931 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.042740 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.013291 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.016874 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.151745 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.224649 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1022 3319 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 1450 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::0 45 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 109 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::2 648 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::3 26 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::4 2491 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 280 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 987 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.202576 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.088501 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 3104105 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 3104105 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 54552 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 64413 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 118965 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 64873 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 64873 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 8421 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 8421 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 54552 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 72834 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 127386 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 54552 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 72834 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 127386 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 364 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 699 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 211 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 211 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 575 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 910 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 575 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 910 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24852997 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 26184000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 51036997 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15318999 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 15318999 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 24852997 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 41502999 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 66355996 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 24852997 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 41502999 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 66355996 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 54887 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 64777 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 119664 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 64873 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 64873 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 8632 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 8632 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 54887 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 73409 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 128296 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 54887 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 73409 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 128296 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.006103 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.005619 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.005841 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.024444 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.024444 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.006103 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.007833 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.007093 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.006103 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.007833 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.007093 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74188.050746 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71934.065934 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 73014.301860 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72601.890995 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72601.890995 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74188.050746 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72179.128696 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 72918.676923 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74188.050746 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72179.128696 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 72918.676923 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 2973 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 134 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 22.186567 # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 50 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 50 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 50 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 285 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 341 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 626 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 5385 # number of HardPFReq MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_misses::total 5385 # number of HardPFReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 211 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 211 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 285 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 552 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 837 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 285 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 552 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 5385 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 6222 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20480998 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 22050750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 42531748 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 326822301 # number of HardPFReq MSHR miss cycles
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 326822301 # number of HardPFReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13544999 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13544999 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20480998 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 35595749 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 56076747 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20480998 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 35595749 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 326822301 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 382899048 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005192 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.005264 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.005231 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.024444 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.024444 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005192 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.007520 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.006524 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005192 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.007520 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.048497 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71863.150877 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64664.956012 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67942.089457 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 60691.235097 # average HardPFReq mshr miss latency
|
|
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 60691.235097 # average HardPFReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64194.308057 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64194.308057 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71863.150877 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64485.052536 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66997.308244 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71863.150877 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64485.052536 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 60691.235097 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61539.544841 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 72897 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.503812 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 41115488 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 73409 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 560.087837 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 471699000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.503812 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999031 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999031 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 220 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 82528199 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 82528199 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 28728737 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 28728737 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 12341838 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 12341838 # number of WriteReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 361 # number of SoftPFReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::total 361 # number of SoftPFReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 22145 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 22145 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 41070575 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 41070575 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 41070936 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 41070936 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 89075 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 89075 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 22449 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 22449 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 121 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 121 # number of SoftPFReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 262 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 262 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 111524 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 111524 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 111645 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 111645 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 824002993 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 824002993 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 221780748 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 221780748 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2327000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 2327000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 1045783741 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 1045783741 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 1045783741 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 1045783741 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 28817812 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 28817812 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 482 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 482 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 41182099 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 41182099 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 41182581 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 41182581 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003091 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.003091 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001816 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.001816 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.251037 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.251037 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011693 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011693 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.002708 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.002708 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.002711 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.002711 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9250.665091 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 9250.665091 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9879.315248 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 9879.315248 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8881.679389 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8881.679389 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 9377.207964 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 9377.207964 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 9367.045018 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 9367.045018 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 279 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 7362 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 531 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 93 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 13.864407 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 64873 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 64873 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24343 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 24343 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 13890 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 13890 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 262 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 262 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 38233 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 38233 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 38233 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 38233 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64732 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 64732 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8559 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 8559 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 118 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 118 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 73291 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 73291 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 73409 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 73409 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 483955005 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 483955005 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 74150498 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 74150498 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1036250 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1036250 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 558105503 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 558105503 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 559141753 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 559141753 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002246 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002246 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000692 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.244813 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.244813 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001780 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001783 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.001783 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7476.286921 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7476.286921 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8663.453441 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8663.453441 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8781.779661 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8781.779661 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7614.925475 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 7614.925475 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7616.801114 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 7616.801114 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|