c4e91289ae
This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2168 lines
250 KiB
Text
2168 lines
250 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.539695 # Number of seconds simulated
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sim_ticks 2539695141000 # Number of ticks simulated
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final_tick 2539695141000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 55026 # Simulator instruction rate (inst/s)
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host_op_rate 66292 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2316696588 # Simulator tick rate (ticks/s)
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host_mem_usage 466732 # Number of bytes of host memory used
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host_seconds 1096.26 # Real time elapsed on the host
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sim_insts 60322278 # Number of instructions simulated
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sim_ops 72673006 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.dtb.walker 960 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 471296 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 3922776 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 576 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 314048 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 5167104 # Number of bytes read from this memory
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system.physmem.bytes_read::total 130987352 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 471296 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 314048 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 785344 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 3775232 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 1328636 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 1687436 # Number of bytes written to this memory
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system.physmem.bytes_written::total 6791304 # Number of bytes written to this memory
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system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.dtb.walker 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 7364 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 61319 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.dtb.walker 9 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 4907 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 80736 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 15293167 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 58988 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 332159 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 421859 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 813006 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.clcd 47687034 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.dtb.walker 378 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 185572 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 1544585 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 227 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 123656 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 2034537 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 51576014 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 185572 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 123656 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 309228 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1486490 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 523148 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 664425 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2674063 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1486490 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.clcd 47687034 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 378 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 185572 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 2067733 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 227 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 123656 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 2698962 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 54250077 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 15293167 # Number of read requests accepted
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system.physmem.writeReqs 813006 # Number of write requests accepted
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system.physmem.readBursts 15293167 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 813006 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 975220032 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 3542656 # Total number of bytes read from write queue
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system.physmem.bytesWritten 6827904 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 130987352 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 6791304 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 55354 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 706297 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 4647 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 954783 # Per bank write bursts
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system.physmem.perBankRdBursts::1 950591 # Per bank write bursts
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system.physmem.perBankRdBursts::2 950729 # Per bank write bursts
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system.physmem.perBankRdBursts::3 950904 # Per bank write bursts
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system.physmem.perBankRdBursts::4 954888 # Per bank write bursts
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system.physmem.perBankRdBursts::5 951868 # Per bank write bursts
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system.physmem.perBankRdBursts::6 951800 # Per bank write bursts
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system.physmem.perBankRdBursts::7 951730 # Per bank write bursts
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system.physmem.perBankRdBursts::8 955391 # Per bank write bursts
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system.physmem.perBankRdBursts::9 951917 # Per bank write bursts
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system.physmem.perBankRdBursts::10 951458 # Per bank write bursts
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system.physmem.perBankRdBursts::11 951066 # Per bank write bursts
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system.physmem.perBankRdBursts::12 955340 # Per bank write bursts
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system.physmem.perBankRdBursts::13 951888 # Per bank write bursts
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system.physmem.perBankRdBursts::14 951979 # Per bank write bursts
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system.physmem.perBankRdBursts::15 951481 # Per bank write bursts
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system.physmem.perBankWrBursts::0 6606 # Per bank write bursts
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system.physmem.perBankWrBursts::1 6389 # Per bank write bursts
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system.physmem.perBankWrBursts::2 6527 # Per bank write bursts
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system.physmem.perBankWrBursts::3 6560 # Per bank write bursts
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system.physmem.perBankWrBursts::4 6487 # Per bank write bursts
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system.physmem.perBankWrBursts::5 6764 # Per bank write bursts
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system.physmem.perBankWrBursts::6 6744 # Per bank write bursts
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system.physmem.perBankWrBursts::7 6672 # Per bank write bursts
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system.physmem.perBankWrBursts::8 7003 # Per bank write bursts
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system.physmem.perBankWrBursts::9 6796 # Per bank write bursts
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system.physmem.perBankWrBursts::10 6466 # Per bank write bursts
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system.physmem.perBankWrBursts::11 6118 # Per bank write bursts
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system.physmem.perBankWrBursts::12 7066 # Per bank write bursts
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system.physmem.perBankWrBursts::13 6690 # Per bank write bursts
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system.physmem.perBankWrBursts::14 6968 # Per bank write bursts
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system.physmem.perBankWrBursts::15 6830 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 2539694027000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 18 # Read request sizes (log2)
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system.physmem.readPktSize::3 15138826 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 154323 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 754018 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 58988 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 1062880 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 1005296 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 961490 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 1064387 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 969141 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1032129 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 2687855 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 2599195 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 3397795 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 112262 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 102458 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 95445 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 91862 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 18918 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 18413 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 18221 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 49 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 11 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 294 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 289 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 285 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 282 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 278 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 276 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 275 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 273 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 272 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 269 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 266 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 265 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 265 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 262 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 260 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 3217 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 3674 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 4739 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 6036 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 6170 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 6116 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 6047 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 6096 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 6085 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 6255 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 6252 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 5932 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 5912 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 6306 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 5873 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 5906 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 6094 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 5789 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 56 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 26 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 12 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 1008813 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 973.468756 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 909.284641 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 200.732372 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 22320 2.21% 2.21% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 20114 1.99% 4.21% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 8797 0.87% 5.08% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 2199 0.22% 5.30% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::512-639 2055 0.20% 5.50% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::640-767 1694 0.17% 5.67% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::768-895 9190 0.91% 6.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-1023 817 0.08% 6.66% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 941627 93.34% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 1008813 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 6078 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 2507.042448 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 47447.723031 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-65535 6050 99.54% 99.54% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::65536-131071 3 0.05% 99.59% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::131072-196607 8 0.13% 99.72% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::196608-262143 5 0.08% 99.80% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::393216-458751 1 0.02% 99.82% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.84% # Reads before turning the bus around for writes
|
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system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.85% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::983040-1.04858e+06 2 0.03% 99.88% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 6 0.10% 99.98% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 6078 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 6078 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::mean 17.552813 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::gmean 17.369881 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::stdev 2.322612 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::1 5 0.08% 0.08% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::2 4 0.07% 0.15% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::3 4 0.07% 0.21% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::4 4 0.07% 0.28% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::5 2 0.03% 0.31% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::6 2 0.03% 0.35% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::7 3 0.05% 0.39% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::8 1 0.02% 0.41% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::9 6 0.10% 0.51% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::10 3 0.05% 0.56% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::11 2 0.03% 0.59% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::12 3 0.05% 0.64% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::13 3 0.05% 0.69% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::14 2 0.03% 0.72% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::15 13 0.21% 0.94% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16 2782 45.77% 46.71% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::17 46 0.76% 47.47% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::18 1401 23.05% 70.52% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::19 1370 22.54% 93.06% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20 152 2.50% 95.56% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::21 75 1.23% 96.79% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::22 36 0.59% 97.38% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::23 22 0.36% 97.75% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24 24 0.39% 98.14% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::25 25 0.41% 98.55% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::26 13 0.21% 98.77% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::27 15 0.25% 99.01% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28 16 0.26% 99.28% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::29 12 0.20% 99.47% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::30 9 0.15% 99.62% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::31 11 0.18% 99.80% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32 12 0.20% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 6078 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 392436805250 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 678145799000 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 76189065000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 25754.14 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 44504.14 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 383.99 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 2.69 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 51.58 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 3.02 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 6.40 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 14.87 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 14244486 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 91200 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 85.47 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 157684.51 # Average gap between requests
|
|
system.physmem.pageHitRate 93.43 # Row buffer hit rate, read and write combined
|
|
system.physmem.memoryStateTime::IDLE 2193361967750 # Time in different power states
|
|
system.physmem.memoryStateTime::REF 84805760000 # Time in different power states
|
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT 261520412250 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
|
|
system.membus.trans_dist::ReadReq 16345693 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 16345693 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 763357 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 763357 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 58988 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 4647 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 4647 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 131549 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 131549 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383044 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3780 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885020 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 4271848 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 34549480 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2390454 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16668128 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::total 19066210 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 140176738 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 217843 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 217843 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 217843 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 1488348000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 1500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 3508000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer6.occupancy 17564779000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 4755343440 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 37440252152 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 1.5 # Layer utilization (%)
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.l2c.tags.replacements 64097 # number of replacements
|
|
system.l2c.tags.tagsinuse 51403.492359 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 1900046 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 129489 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 14.673416 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 2528369126500 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 37092.927950 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.dtb.walker 9.579992 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000251 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 5418.531577 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 3300.356905 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.dtb.walker 6.423602 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 2630.879076 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 2944.793006 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.565993 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000146 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.082680 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.050359 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000098 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.040144 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.044934 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.784355 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_blocks::1024 65379 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 434 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 3142 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::3 5950 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::4 55813 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.997604 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 18888451 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 18888451 # Number of data accesses
|
|
system.l2c.ReadReq_hits::cpu0.dtb.walker 27538 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.itb.walker 7475 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.inst 477559 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.data 174980 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.dtb.walker 30012 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.itb.walker 8090 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 496617 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.data 210611 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 1432882 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 606482 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 606482 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 33 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu1.data 1 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 55610 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 57109 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 112719 # number of ReadExReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 27538 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 7475 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 477559 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 230590 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 30012 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 8090 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 496617 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 267720 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1545601 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 27538 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 7475 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 477559 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 230590 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 30012 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 8090 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 496617 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 267720 # number of overall hits
|
|
system.l2c.overall_hits::total 1545601 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.dtb.walker 15 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.inst 7255 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.data 6034 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.dtb.walker 9 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.inst 4911 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.data 4500 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 22725 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_misses::cpu0.data 1367 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 1537 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 2904 # number of UpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 56126 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 77166 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 133292 # number of ReadExReq misses
|
|
system.l2c.demand_misses::cpu0.dtb.walker 15 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.inst 7255 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 62160 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.dtb.walker 9 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 4911 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 81666 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 156017 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.dtb.walker 15 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.inst 7255 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 62160 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.dtb.walker 9 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 4911 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 81666 # number of overall misses
|
|
system.l2c.overall_misses::total 156017 # number of overall misses
|
|
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1563750 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 82000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.inst 521104500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.data 442572744 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 713750 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.inst 356046000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.data 335278744 # number of ReadReq miss cycles
|
|
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|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 166949053750 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 7705500500 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 9339419914 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::total 17044920414 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6123500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 91411866750 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 92575983914 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 183993974164 # number of overall MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000544 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000134 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014952 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.033125 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000300 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009784 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020836 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.015567 # mshr miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.987717 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989697 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.988764 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.502309 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.574686 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.541813 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000544 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000134 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014952 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.212202 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000300 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009784 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.233690 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.091649 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000544 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000134 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014952 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.212202 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000300 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009784 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.233690 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.091649 # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 91950 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59255.724928 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60904.351901 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59932.341553 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62130.911200 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 60432.454566 # average ReadReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10003.926116 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.252440 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.098829 # average UpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59183.401294 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62336.364578 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 61008.728881 # average ReadExReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 91950 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59255.724928 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 59349.507018 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59932.341553 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62325.086383 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 60924.998737 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 91950 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59255.724928 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 59349.507018 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59932.341553 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62325.086383 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 60924.998737 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
|
system.toL2Bus.trans_dist::ReadReq 2673184 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 2673184 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 763357 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 763357 # Transaction distribution
|
|
system.toL2Bus.trans_dist::Writeback 606482 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 2937 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 2940 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 246011 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 246011 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1973853 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5791552 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42247 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 136455 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 7944107 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 63133312 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85325794 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 62264 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 230296 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 148751666 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 33359 # Total snoops (count)
|
|
system.toL2Bus.snoop_fanout::samples 2344441 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::5 2344441 100.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 2344441 # Request fanout histogram
|
|
system.toL2Bus.reqLayer0.occupancy 4954098182 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 4446552172 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 4477877910 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 26748853 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 79493732 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.trans_dist::ReadReq 16322162 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 16322162 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 8176 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 8176 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7928 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 520 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1028 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 2383044 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 32660676 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15856 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 2390454 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 123500982 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 3969000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 520000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 520000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 2374868000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 38127481848 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
|
|
system.cpu0.branchPred.lookups 7736387 # Number of BP lookups
|
|
system.cpu0.branchPred.condPredicted 5741528 # Number of conditional branches predicted
|
|
system.cpu0.branchPred.condIncorrect 324689 # Number of conditional branches incorrect
|
|
system.cpu0.branchPred.BTBLookups 4736478 # Number of BTB lookups
|
|
system.cpu0.branchPred.BTBHits 3796485 # Number of BTB hits
|
|
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu0.branchPred.BTBHitPct 80.154178 # BTB Hit Percentage
|
|
system.cpu0.branchPred.usedRAS 808967 # Number of times the RAS was used to get a target.
|
|
system.cpu0.branchPred.RASInCorrect 22406 # Number of incorrect RAS predictions.
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dtb.read_hits 27184101 # DTB read hits
|
|
system.cpu0.dtb.read_misses 37692 # DTB read misses
|
|
system.cpu0.dtb.write_hits 5601213 # DTB write hits
|
|
system.cpu0.dtb.write_misses 10069 # DTB write misses
|
|
system.cpu0.dtb.flush_tlb 510 # Number of times complete TLB was flushed
|
|
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dtb.flush_tlb_mva_asid 726 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dtb.flush_entries 5493 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dtb.align_faults 558 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dtb.prefetch_faults 288 # Number of TLB faults due to prefetch
|
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dtb.perms_faults 698 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dtb.read_accesses 27221793 # DTB read accesses
|
|
system.cpu0.dtb.write_accesses 5611282 # DTB write accesses
|
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dtb.hits 32785314 # DTB hits
|
|
system.cpu0.dtb.misses 47761 # DTB misses
|
|
system.cpu0.dtb.accesses 32833075 # DTB accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.itb.inst_hits 5349776 # ITB inst hits
|
|
system.cpu0.itb.inst_misses 7612 # ITB inst misses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.flush_tlb 510 # Number of times complete TLB was flushed
|
|
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.itb.flush_tlb_mva_asid 726 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
|
|
system.cpu0.itb.flush_entries 2622 # Number of entries that have been flushed from TLB
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.itb.perms_faults 2424 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.inst_accesses 5357388 # ITB inst accesses
|
|
system.cpu0.itb.hits 5349776 # DTB hits
|
|
system.cpu0.itb.misses 7612 # DTB misses
|
|
system.cpu0.itb.accesses 5357388 # DTB accesses
|
|
system.cpu0.numCycles 234157878 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.fetch.icacheStallCycles 14748705 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu0.fetch.Insts 42201957 # Number of instructions fetch has processed
|
|
system.cpu0.fetch.Branches 7736387 # Number of branches that fetch encountered
|
|
system.cpu0.fetch.predictedBranches 4605452 # Number of branches that fetch has predicted taken
|
|
system.cpu0.fetch.Cycles 215146781 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu0.fetch.SquashCycles 898208 # Number of cycles fetch has spent squashing
|
|
system.cpu0.fetch.TlbCycles 106243 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu0.fetch.MiscStallCycles 1405 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu0.fetch.PendingDrainCycles 1864 # Number of cycles fetch has spent waiting on pipes to drain
|
|
system.cpu0.fetch.PendingTrapStallCycles 95051 # Number of stall cycles due to pending traps
|
|
system.cpu0.fetch.PendingQuiesceStallCycles 1850622 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu0.fetch.IcacheWaitRetryStallCycles 160 # Number of stall cycles due to full MSHR
|
|
system.cpu0.fetch.CacheLines 5346983 # Number of cache lines fetched
|
|
system.cpu0.fetch.IcacheSquashes 204760 # Number of outstanding Icache misses that were squashed
|
|
system.cpu0.fetch.ItlbSquashes 2833 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu0.fetch.rateDist::samples 232399808 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::mean 0.216000 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::stdev 1.156571 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::0 222777653 95.86% 95.86% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::1 886693 0.38% 96.24% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::2 957710 0.41% 96.65% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::3 1031526 0.44% 97.10% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::4 1201262 0.52% 97.61% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::5 716459 0.31% 97.92% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::6 1131800 0.49% 98.41% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::7 450199 0.19% 98.60% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::8 3246506 1.40% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::total 232399808 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.branchRate 0.033039 # Number of branch fetches per cycle
|
|
system.cpu0.fetch.rate 0.180229 # Number of inst fetches per cycle
|
|
system.cpu0.decode.IdleCycles 12178110 # Number of cycles decode is idle
|
|
system.cpu0.decode.BlockedCycles 212389955 # Number of cycles decode is blocked
|
|
system.cpu0.decode.RunCycles 6147086 # Number of cycles decode is running
|
|
system.cpu0.decode.UnblockCycles 1310186 # Number of cycles decode is unblocking
|
|
system.cpu0.decode.SquashCycles 372224 # Number of cycles decode is squashing
|
|
system.cpu0.decode.BranchResolved 973042 # Number of times decode resolved a branch
|
|
system.cpu0.decode.BranchMispred 78155 # Number of times decode detected a branch misprediction
|
|
system.cpu0.decode.DecodedInsts 44916036 # Number of instructions handled by decode
|
|
system.cpu0.decode.SquashedInsts 260169 # Number of squashed instructions handled by decode
|
|
system.cpu0.rename.SquashCycles 372224 # Number of cycles rename is squashing
|
|
system.cpu0.rename.IdleCycles 12790792 # Number of cycles rename is idle
|
|
system.cpu0.rename.BlockCycles 53545394 # Number of cycles rename is blocking
|
|
system.cpu0.rename.serializeStallCycles 30504571 # count of cycles rename stalled for serializing inst
|
|
system.cpu0.rename.RunCycles 6768689 # Number of cycles rename is running
|
|
system.cpu0.rename.UnblockCycles 128415973 # Number of cycles rename is unblocking
|
|
system.cpu0.rename.RenamedInsts 43504199 # Number of instructions processed by rename
|
|
system.cpu0.rename.ROBFullEvents 1378 # Number of times rename has blocked due to ROB full
|
|
system.cpu0.rename.IQFullEvents 95402427 # Number of times rename has blocked due to IQ full
|
|
system.cpu0.rename.LQFullEvents 124537502 # Number of times rename has blocked due to LQ full
|
|
system.cpu0.rename.SQFullEvents 1839930 # Number of times rename has blocked due to SQ full
|
|
system.cpu0.rename.RenamedOperands 46109442 # Number of destination operands rename has renamed
|
|
system.cpu0.rename.RenameLookups 200228601 # Number of register rename lookups that rename has made
|
|
system.cpu0.rename.int_rename_lookups 53009049 # Number of integer rename lookups
|
|
system.cpu0.rename.fp_rename_lookups 5261 # Number of floating rename lookups
|
|
system.cpu0.rename.CommittedMaps 36340147 # Number of HB maps that are committed
|
|
system.cpu0.rename.UndoneMaps 9769295 # Number of HB maps that are undone due to squashing
|
|
system.cpu0.rename.serializingInsts 578634 # count of serializing insts renamed
|
|
system.cpu0.rename.tempSerializingInsts 493652 # count of temporary serializing insts renamed
|
|
system.cpu0.rename.skidInsts 7443860 # count of insts added to the skid buffer
|
|
system.cpu0.memDep0.insertedLoads 7970278 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.insertedStores 6245265 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.conflictingLoads 1090249 # Number of conflicting loads.
|
|
system.cpu0.memDep0.conflictingStores 1688574 # Number of conflicting stores.
|
|
system.cpu0.iq.iqInstsAdded 41187030 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu0.iq.iqNonSpecInstsAdded 989826 # Number of non-speculative instructions added to the IQ
|
|
system.cpu0.iq.iqInstsIssued 58971927 # Number of instructions issued
|
|
system.cpu0.iq.iqSquashedInstsIssued 58739 # Number of squashed instructions issued
|
|
system.cpu0.iq.iqSquashedInstsExamined 7127220 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu0.iq.iqSquashedOperandsExamined 15644672 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu0.iq.iqSquashedNonSpecRemoved 268943 # Number of squashed non-spec instructions that were removed
|
|
system.cpu0.iq.issued_per_cycle::samples 232399808 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::mean 0.253752 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::stdev 0.958915 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::0 212110796 91.27% 91.27% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::1 6244814 2.69% 93.96% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::2 2921782 1.26% 95.21% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::3 2401444 1.03% 96.25% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::4 6174292 2.66% 98.90% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::5 1067597 0.46% 99.36% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::6 901998 0.39% 99.75% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::7 384604 0.17% 99.92% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::8 192481 0.08% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::total 232399808 # Number of insts issued each cycle
|
|
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntAlu 115073 2.28% 2.28% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntMult 2 0.00% 2.28% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.28% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.28% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.28% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.28% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.28% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.28% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.28% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.28% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.28% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.28% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.28% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.28% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.28% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.28% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.28% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.28% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.28% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.28% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.28% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.28% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.28% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.28% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.28% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.28% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.28% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.28% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.28% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemRead 4670641 92.37% 94.64% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemWrite 270791 5.36% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.FU_type_0::No_OpClass 15020 0.03% 0.03% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntAlu 25465355 43.18% 43.21% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntMult 47791 0.08% 43.29% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 43.29% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 43.29% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 43.29% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 43.29% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 43.29% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 43.29% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 43.29% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 43.29% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 43.29% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 43.29% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 43.29% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 43.29% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 43.29% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 43.29% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 43.29% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 43.29% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 43.29% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 43.29% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.29% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.29% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.29% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.29% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.29% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMisc 896 0.00% 43.29% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 43.29% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 43.29% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.29% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemRead 27510585 46.65% 89.94% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemWrite 5932280 10.06% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::total 58971927 # Type of FU issued
|
|
system.cpu0.iq.rate 0.251847 # Inst issue rate
|
|
system.cpu0.iq.fu_busy_cnt 5056507 # FU busy when requested
|
|
system.cpu0.iq.fu_busy_rate 0.085744 # FU busy rate (busy events/executed inst)
|
|
system.cpu0.iq.int_inst_queue_reads 355447115 # Number of integer instruction queue reads
|
|
system.cpu0.iq.int_inst_queue_writes 49321417 # Number of integer instruction queue writes
|
|
system.cpu0.iq.int_inst_queue_wakeup_accesses 38218166 # Number of integer instruction queue wakeup accesses
|
|
system.cpu0.iq.fp_inst_queue_reads 11793 # Number of floating instruction queue reads
|
|
system.cpu0.iq.fp_inst_queue_writes 6394 # Number of floating instruction queue writes
|
|
system.cpu0.iq.fp_inst_queue_wakeup_accesses 5095 # Number of floating instruction queue wakeup accesses
|
|
system.cpu0.iq.int_alu_accesses 64007055 # Number of integer alu accesses
|
|
system.cpu0.iq.fp_alu_accesses 6359 # Number of floating point alu accesses
|
|
system.cpu0.iew.lsq.thread0.forwLoads 225424 # Number of loads that had data forwarded from stores
|
|
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.squashedLoads 1448099 # Number of loads squashed
|
|
system.cpu0.iew.lsq.thread0.ignoredResponses 2516 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu0.iew.lsq.thread0.memOrderViolation 24796 # Number of memory ordering violations
|
|
system.cpu0.iew.lsq.thread0.squashedStores 671952 # Number of stores squashed
|
|
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu0.iew.lsq.thread0.rescheduledLoads 17102895 # Number of loads that were rescheduled
|
|
system.cpu0.iew.lsq.thread0.cacheBlocked 3149110 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu0.iew.iewSquashCycles 372224 # Number of cycles IEW is squashing
|
|
system.cpu0.iew.iewBlockCycles 50935329 # Number of cycles IEW is blocking
|
|
system.cpu0.iew.iewUnblockCycles 1903194 # Number of cycles IEW is unblocking
|
|
system.cpu0.iew.iewDispatchedInsts 42289333 # Number of instructions dispatched to IQ
|
|
system.cpu0.iew.iewDispSquashedInsts 78950 # Number of squashed instructions skipped by dispatch
|
|
system.cpu0.iew.iewDispLoadInsts 7970278 # Number of dispatched load instructions
|
|
system.cpu0.iew.iewDispStoreInsts 6245265 # Number of dispatched store instructions
|
|
system.cpu0.iew.iewDispNonSpecInsts 710795 # Number of dispatched non-speculative instructions
|
|
system.cpu0.iew.iewIQFullEvents 138182 # Number of times the IQ has become full, causing a stall
|
|
system.cpu0.iew.iewLSQFullEvents 1696089 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu0.iew.memOrderViolationEvents 24796 # Number of memory order violations
|
|
system.cpu0.iew.predictedTakenIncorrect 159500 # Number of branches that were predicted taken incorrectly
|
|
system.cpu0.iew.predictedNotTakenIncorrect 133057 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu0.iew.branchMispredicts 292557 # Number of branch mispredicts detected at execute
|
|
system.cpu0.iew.iewExecutedInsts 58565137 # Number of executed instructions
|
|
system.cpu0.iew.iewExecLoadInsts 27348453 # Number of load instructions executed
|
|
system.cpu0.iew.iewExecSquashedInsts 359214 # Number of squashed instructions skipped in execute
|
|
system.cpu0.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu0.iew.exec_nop 112477 # number of nop insts executed
|
|
system.cpu0.iew.exec_refs 33216509 # number of memory reference insts executed
|
|
system.cpu0.iew.exec_branches 5651382 # Number of branches executed
|
|
system.cpu0.iew.exec_stores 5868056 # Number of stores executed
|
|
system.cpu0.iew.exec_rate 0.250110 # Inst execution rate
|
|
system.cpu0.iew.wb_sent 55395790 # cumulative count of insts sent to commit
|
|
system.cpu0.iew.wb_count 38223261 # cumulative count of insts written-back
|
|
system.cpu0.iew.wb_producers 21614386 # num instructions producing a value
|
|
system.cpu0.iew.wb_consumers 38462259 # num instructions consuming a value
|
|
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu0.iew.wb_rate 0.163237 # insts written-back per cycle
|
|
system.cpu0.iew.wb_fanout 0.561964 # average fanout of values written-back
|
|
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu0.commit.commitSquashedInsts 7051288 # The number of squashed insts skipped by commit
|
|
system.cpu0.commit.commitNonSpecStalls 720883 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu0.commit.branchMispredicts 247682 # The number of times a branch was mispredicted
|
|
system.cpu0.commit.committed_per_cycle::samples 231240606 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::mean 0.150761 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::stdev 0.850016 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::0 218744105 94.60% 94.60% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::1 6302358 2.73% 97.32% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::2 1708730 0.74% 98.06% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::3 1054896 0.46% 98.52% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::4 648771 0.28% 98.80% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::5 578680 0.25% 99.05% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::6 445136 0.19% 99.24% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::7 245162 0.11% 99.35% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::8 1512768 0.65% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::total 231240606 # Number of insts commited each cycle
|
|
system.cpu0.commit.committedInsts 29065490 # Number of instructions committed
|
|
system.cpu0.commit.committedOps 34862084 # Number of ops (including micro ops) committed
|
|
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu0.commit.refs 12095492 # Number of memory references committed
|
|
system.cpu0.commit.loads 6522179 # Number of loads committed
|
|
system.cpu0.commit.membars 193065 # Number of memory barriers committed
|
|
system.cpu0.commit.branches 4958543 # Number of branches committed
|
|
system.cpu0.commit.fp_insts 5094 # Number of committed floating point instructions.
|
|
system.cpu0.commit.int_insts 30770331 # Number of committed integer instructions.
|
|
system.cpu0.commit.function_calls 472637 # Number of function calls committed.
|
|
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IntAlu 22721291 65.17% 65.17% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IntMult 44405 0.13% 65.30% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 65.30% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 65.30% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 65.30% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 65.30% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 65.30% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 65.30% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 65.30% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 65.30% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 65.30% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 65.30% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 65.30% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 65.30% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 65.30% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 65.30% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 65.30% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 65.30% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 65.30% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 65.30% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 65.30% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 65.30% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 65.30% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 65.30% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 65.30% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatMisc 896 0.00% 65.30% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 65.30% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.30% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.30% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::MemRead 6522179 18.71% 84.01% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::MemWrite 5573313 15.99% 100.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::total 34862084 # Class of committed instruction
|
|
system.cpu0.commit.bw_lim_events 1512768 # number cycles where commit BW limit reached
|
|
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu0.rob.rob_reads 270737391 # The number of ROB reads
|
|
system.cpu0.rob.rob_writes 84952654 # The number of ROB writes
|
|
system.cpu0.timesIdled 265059 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu0.idleCycles 1758070 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu0.quiesceCycles 2270312982 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu0.committedInsts 28998871 # Number of Instructions Simulated
|
|
system.cpu0.committedOps 34795465 # Number of Ops (including micro ops) Simulated
|
|
system.cpu0.cpi 8.074724 # CPI: Cycles Per Instruction
|
|
system.cpu0.cpi_total 8.074724 # CPI: Total CPI of All Threads
|
|
system.cpu0.ipc 0.123843 # IPC: Instructions Per Cycle
|
|
system.cpu0.ipc_total 0.123843 # IPC: Total IPC of All Threads
|
|
system.cpu0.int_regfile_reads 66418764 # number of integer regfile reads
|
|
system.cpu0.int_regfile_writes 24158486 # number of integer regfile writes
|
|
system.cpu0.fp_regfile_reads 44743 # number of floating regfile reads
|
|
system.cpu0.fp_regfile_writes 41780 # number of floating regfile writes
|
|
system.cpu0.cc_regfile_reads 196661933 # number of cc regfile reads
|
|
system.cpu0.cc_regfile_writes 15655112 # number of cc regfile writes
|
|
system.cpu0.misc_regfile_reads 292292897 # number of misc regfile reads
|
|
system.cpu0.misc_regfile_writes 565980 # number of misc regfile writes
|
|
system.cpu0.icache.tags.replacements 986757 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 511.592826 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 9965260 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 987269 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 10.093764 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 6651821250 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 184.507996 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_blocks::cpu1.inst 327.084830 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.360367 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.638838 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.999205 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 157 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 12017349 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 12017349 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 4823854 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::cpu1.inst 5141406 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 9965260 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 4823854 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::cpu1.inst 5141406 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 9965260 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 4823854 # number of overall hits
|
|
system.cpu0.icache.overall_hits::cpu1.inst 5141406 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 9965260 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 523011 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::cpu1.inst 541799 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 1064810 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 523011 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::cpu1.inst 541799 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 1064810 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 523011 # number of overall misses
|
|
system.cpu0.icache.overall_misses::cpu1.inst 541799 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 1064810 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7244933790 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 7308182079 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 14553115869 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 7244933790 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu1.inst 7308182079 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 14553115869 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 7244933790 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu1.inst 7308182079 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 14553115869 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 5346865 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::cpu1.inst 5683205 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 11030070 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 5346865 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::cpu1.inst 5683205 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 11030070 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 5346865 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu1.inst 5683205 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 11030070 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097816 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.095333 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.096537 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097816 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.095333 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.096537 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097816 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.095333 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.096537 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13852.354520 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13488.733052 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 13667.335834 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13852.354520 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13488.733052 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 13667.335834 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13852.354520 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13488.733052 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 13667.335834 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 4607 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 283 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.279152 # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 37777 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39754 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::total 77531 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu0.inst 37777 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu1.inst 39754 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::total 77531 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu0.inst 37777 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu1.inst 39754 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::total 77531 # number of overall MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 485234 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 502045 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 987279 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 485234 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu1.inst 502045 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 987279 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 485234 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu1.inst 502045 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 987279 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5896477037 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5947728017 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 11844205054 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5896477037 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5947728017 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 11844205054 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5896477037 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5947728017 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 11844205054 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8530500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8530500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8530500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::total 8530500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090751 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.088338 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.089508 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090751 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.088338 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.089508 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090751 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.088338 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.089508 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12151.821672 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11847.001797 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11996.816557 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12151.821672 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11847.001797 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11996.816557 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12151.821672 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11847.001797 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11996.816557 # average overall mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.dcache.tags.replacements 641624 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 511.993418 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 19749835 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 642136 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 30.756467 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 42094250 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 133.332182 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_blocks::cpu1.data 378.661236 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.260414 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.739573 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 293 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 95284916 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 95284916 # Number of data accesses
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 5852905 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::cpu1.data 6194424 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 12047329 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 3505923 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu1.data 3637478 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 7143401 # number of WriteReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 35429 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 29531 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::total 64960 # number of SoftPFReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 110357 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 133056 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 243413 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 112492 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 135154 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 247646 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 9358828 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::cpu1.data 9831902 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 19190730 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 9394257 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::cpu1.data 9861433 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 19255690 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 296259 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::cpu1.data 395495 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 691754 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 1362667 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu1.data 1717725 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 3080392 # number of WriteReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 74316 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 54156 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::total 128472 # number of SoftPFReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6370 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6955 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 13325 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 1 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 1658926 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::cpu1.data 2113220 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 3772146 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 1733242 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::cpu1.data 2167376 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 3900618 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4388776307 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 5728170629 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 10116946936 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 57800783004 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 86624659870 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 144425442874 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92286740 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 93793740 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 186080480 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 26000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 13000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 39000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 62189559311 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu1.data 92352830499 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 154542389810 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 62189559311 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu1.data 92352830499 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 154542389810 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6149164 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::cpu1.data 6589919 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 12739083 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4868590 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu1.data 5355203 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 10223793 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 109745 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 83687 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::total 193432 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 116727 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 140011 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 256738 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 112494 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 135155 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 247649 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 11017754 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::cpu1.data 11945122 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 22962876 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 11127499 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu1.data 12028809 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 23156308 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.048179 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.060015 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.054302 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.279889 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.320758 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.301296 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.677170 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.647126 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.664171 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054572 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049675 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.051901 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000018 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000007 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000012 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.150568 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.176911 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.164271 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.155762 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.180182 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.168447 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14813.984746 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14483.547527 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14625.064598 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42417.393981 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 50429.876651 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 46885.410322 # average WriteReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14487.714286 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13485.800144 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13964.763977 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13000 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37487.844130 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 43702.421186 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 40969.355325 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35880.482536 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 42610.433307 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 39619.975555 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 200600 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 41919 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 27184 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 783 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7.379341 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets 53.536398 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 606482 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 606482 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 164188 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 218355 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 382543 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1249592 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1581925 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 2831517 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 626 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 765 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1391 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1413780 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu1.data 1800280 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 3214060 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1413780 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu1.data 1800280 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 3214060 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 132071 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 177140 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 309211 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 113075 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 135800 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 248875 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 43244 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 31809 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::total 75053 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5744 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 6190 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11934 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 1 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 245146 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu1.data 312940 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 558086 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 288390 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu1.data 344749 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 633139 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1730710058 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2210787235 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3941497293 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4783325934 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6576818347 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11360144281 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 814553760 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 636336252 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1450890012 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72971510 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72018008 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 144989518 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 22000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 11000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 33000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6514035992 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8787605582 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 15301641574 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7328589752 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9423941834 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 16752531586 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91416176750 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90920349500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182336526250 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 11961680895 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 14731919998 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26693600893 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 103377857645 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 105652269498 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209030127143 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.021478 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026880 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024273 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023225 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025359 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024343 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.394041 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.380095 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.388007 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.049209 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044211 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046483 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000018 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000007 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000012 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.022250 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026198 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.024304 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025917 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028660 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.027342 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13104.391259 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12480.451818 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12746.950442 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42302.241291 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 48430.179286 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45645.984052 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18836.226066 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20004.912195 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19331.539206 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12703.953691 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11634.573183 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12149.280878 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26572.067225 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 28080.800096 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27418.071003 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25412.080003 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27335.661116 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26459.484546 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.branchPred.lookups 8293404 # Number of BP lookups
|
|
system.cpu1.branchPred.condPredicted 6173471 # Number of conditional branches predicted
|
|
system.cpu1.branchPred.condIncorrect 340831 # Number of conditional branches incorrect
|
|
system.cpu1.branchPred.BTBLookups 5168505 # Number of BTB lookups
|
|
system.cpu1.branchPred.BTBHits 4065400 # Number of BTB hits
|
|
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu1.branchPred.BTBHitPct 78.657175 # BTB Hit Percentage
|
|
system.cpu1.branchPred.usedRAS 881063 # Number of times the RAS was used to get a target.
|
|
system.cpu1.branchPred.RASInCorrect 23561 # Number of incorrect RAS predictions.
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 28281448 # DTB read hits
|
|
system.cpu1.dtb.read_misses 40913 # DTB read misses
|
|
system.cpu1.dtb.write_hits 6183126 # DTB write hits
|
|
system.cpu1.dtb.write_misses 14267 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 506 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 713 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 5407 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 858 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 300 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 709 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 28322361 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 6197393 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 34464574 # DTB hits
|
|
system.cpu1.dtb.misses 55180 # DTB misses
|
|
system.cpu1.dtb.accesses 34519754 # DTB accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.itb.inst_hits 5686404 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 8235 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 506 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 713 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 2681 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 2705 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 5694639 # ITB inst accesses
|
|
system.cpu1.itb.hits 5686404 # DTB hits
|
|
system.cpu1.itb.misses 8235 # DTB misses
|
|
system.cpu1.itb.accesses 5694639 # DTB accesses
|
|
system.cpu1.numCycles 237046957 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.fetch.icacheStallCycles 15347817 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu1.fetch.Insts 44890949 # Number of instructions fetch has processed
|
|
system.cpu1.fetch.Branches 8293404 # Number of branches that fetch encountered
|
|
system.cpu1.fetch.predictedBranches 4946463 # Number of branches that fetch has predicted taken
|
|
system.cpu1.fetch.Cycles 217272167 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu1.fetch.SquashCycles 945647 # Number of cycles fetch has spent squashing
|
|
system.cpu1.fetch.TlbCycles 107708 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu1.fetch.MiscStallCycles 1915 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu1.fetch.PendingDrainCycles 1869 # Number of cycles fetch has spent waiting on pipes to drain
|
|
system.cpu1.fetch.PendingTrapStallCycles 102411 # Number of stall cycles due to pending traps
|
|
system.cpu1.fetch.PendingQuiesceStallCycles 2087291 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu1.fetch.IcacheWaitRetryStallCycles 117 # Number of stall cycles due to full MSHR
|
|
system.cpu1.fetch.CacheLines 5683206 # Number of cache lines fetched
|
|
system.cpu1.fetch.IcacheSquashes 214159 # Number of outstanding Icache misses that were squashed
|
|
system.cpu1.fetch.ItlbSquashes 3400 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu1.fetch.rateDist::samples 235393992 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::mean 0.228723 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::stdev 1.188286 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::0 225080067 95.62% 95.62% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::1 947919 0.40% 96.02% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::2 1046635 0.44% 96.47% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::3 1047767 0.45% 96.91% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::4 1244626 0.53% 97.44% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::5 829831 0.35% 97.79% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::6 1297650 0.55% 98.34% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::7 454057 0.19% 98.54% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::8 3445440 1.46% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::total 235393992 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.branchRate 0.034986 # Number of branch fetches per cycle
|
|
system.cpu1.fetch.rate 0.189376 # Number of inst fetches per cycle
|
|
system.cpu1.decode.IdleCycles 12555511 # Number of cycles decode is idle
|
|
system.cpu1.decode.BlockedCycles 214484659 # Number of cycles decode is blocked
|
|
system.cpu1.decode.RunCycles 6498538 # Number of cycles decode is running
|
|
system.cpu1.decode.UnblockCycles 1464859 # Number of cycles decode is unblocking
|
|
system.cpu1.decode.SquashCycles 388308 # Number of cycles decode is squashing
|
|
system.cpu1.decode.BranchResolved 1045918 # Number of times decode resolved a branch
|
|
system.cpu1.decode.BranchMispred 85921 # Number of times decode detected a branch misprediction
|
|
system.cpu1.decode.DecodedInsts 48232824 # Number of instructions handled by decode
|
|
system.cpu1.decode.SquashedInsts 288029 # Number of squashed instructions handled by decode
|
|
system.cpu1.rename.SquashCycles 388308 # Number of cycles rename is squashing
|
|
system.cpu1.rename.IdleCycles 13237235 # Number of cycles rename is idle
|
|
system.cpu1.rename.BlockCycles 54097542 # Number of cycles rename is blocking
|
|
system.cpu1.rename.serializeStallCycles 31323893 # count of cycles rename stalled for serializing inst
|
|
system.cpu1.rename.RunCycles 7199069 # Number of cycles rename is running
|
|
system.cpu1.rename.UnblockCycles 129145928 # Number of cycles rename is unblocking
|
|
system.cpu1.rename.RenamedInsts 46754074 # Number of instructions processed by rename
|
|
system.cpu1.rename.ROBFullEvents 1435 # Number of times rename has blocked due to ROB full
|
|
system.cpu1.rename.IQFullEvents 95558668 # Number of times rename has blocked due to IQ full
|
|
system.cpu1.rename.LQFullEvents 124530529 # Number of times rename has blocked due to LQ full
|
|
system.cpu1.rename.SQFullEvents 2374363 # Number of times rename has blocked due to SQ full
|
|
system.cpu1.rename.RenamedOperands 49626992 # Number of destination operands rename has renamed
|
|
system.cpu1.rename.RenameLookups 215510826 # Number of register rename lookups that rename has made
|
|
system.cpu1.rename.int_rename_lookups 57366811 # Number of integer rename lookups
|
|
system.cpu1.rename.fp_rename_lookups 4976 # Number of floating rename lookups
|
|
system.cpu1.rename.CommittedMaps 39600958 # Number of HB maps that are committed
|
|
system.cpu1.rename.UndoneMaps 10026026 # Number of HB maps that are undone due to squashing
|
|
system.cpu1.rename.serializingInsts 608668 # count of serializing insts renamed
|
|
system.cpu1.rename.tempSerializingInsts 515191 # count of temporary serializing insts renamed
|
|
system.cpu1.rename.skidInsts 8234978 # count of insts added to the skid buffer
|
|
system.cpu1.memDep0.insertedLoads 8452340 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.insertedStores 6808261 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.conflictingLoads 1032874 # Number of conflicting loads.
|
|
system.cpu1.memDep0.conflictingStores 1526046 # Number of conflicting stores.
|
|
system.cpu1.iq.iqInstsAdded 44303656 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu1.iq.iqNonSpecInstsAdded 1049317 # Number of non-speculative instructions added to the IQ
|
|
system.cpu1.iq.iqInstsIssued 62721282 # Number of instructions issued
|
|
system.cpu1.iq.iqSquashedInstsIssued 61124 # Number of squashed instructions issued
|
|
system.cpu1.iq.iqSquashedInstsExamined 7218810 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu1.iq.iqSquashedOperandsExamined 16029580 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu1.iq.iqSquashedNonSpecRemoved 286052 # Number of squashed non-spec instructions that were removed
|
|
system.cpu1.iq.issued_per_cycle::samples 235393992 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::mean 0.266452 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::stdev 0.981415 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::0 213794873 90.82% 90.82% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::1 6639662 2.82% 93.64% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::2 3193505 1.36% 95.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::3 2580445 1.10% 96.10% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::4 6412648 2.72% 98.82% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::5 1155018 0.49% 99.31% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::6 1003845 0.43% 99.74% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::7 407445 0.17% 99.91% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::8 206551 0.09% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::total 235393992 # Number of insts issued each cycle
|
|
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntAlu 146677 2.81% 2.81% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntMult 3 0.00% 2.81% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntDiv 0 0.00% 2.81% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 2.81% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 2.81% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 2.81% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatMult 0 0.00% 2.81% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 2.81% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 2.81% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 2.81% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 2.81% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 2.81% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 2.81% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 2.81% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 2.81% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMult 0 0.00% 2.81% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 2.81% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShift 0 0.00% 2.81% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 2.81% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 2.81% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 2.81% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 2.81% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 2.81% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 2.81% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 2.81% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 2.81% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 2.81% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.81% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 2.81% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemRead 4785763 91.77% 94.59% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemWrite 282272 5.41% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.FU_type_0::No_OpClass 13498 0.02% 0.02% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntAlu 27514443 43.87% 43.89% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntMult 46382 0.07% 43.96% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.96% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.96% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.96% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.96% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.96% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.96% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.96% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.96% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.96% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.96% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.96% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.96% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 43.96% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.96% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.96% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 43.96% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 43.96% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.96% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.96% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.96% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.96% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.96% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.96% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMisc 1213 0.00% 43.97% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.97% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 43.97% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.97% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemRead 28642016 45.67% 89.63% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemWrite 6503730 10.37% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::total 62721282 # Type of FU issued
|
|
system.cpu1.iq.rate 0.264594 # Inst issue rate
|
|
system.cpu1.iq.fu_busy_cnt 5214715 # FU busy when requested
|
|
system.cpu1.iq.fu_busy_rate 0.083141 # FU busy rate (busy events/executed inst)
|
|
system.cpu1.iq.int_inst_queue_reads 366100496 # Number of integer instruction queue reads
|
|
system.cpu1.iq.int_inst_queue_writes 52588764 # Number of integer instruction queue writes
|
|
system.cpu1.iq.int_inst_queue_wakeup_accesses 41277568 # Number of integer instruction queue wakeup accesses
|
|
system.cpu1.iq.fp_inst_queue_reads 11899 # Number of floating instruction queue reads
|
|
system.cpu1.iq.fp_inst_queue_writes 6202 # Number of floating instruction queue writes
|
|
system.cpu1.iq.fp_inst_queue_wakeup_accesses 5156 # Number of floating instruction queue wakeup accesses
|
|
system.cpu1.iq.int_alu_accesses 67916046 # Number of integer alu accesses
|
|
system.cpu1.iq.fp_alu_accesses 6453 # Number of floating point alu accesses
|
|
system.cpu1.iew.lsq.thread0.forwLoads 226153 # Number of loads that had data forwarded from stores
|
|
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.squashedLoads 1459547 # Number of loads squashed
|
|
system.cpu1.iew.lsq.thread0.ignoredResponses 2673 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu1.iew.lsq.thread0.memOrderViolation 24270 # Number of memory ordering violations
|
|
system.cpu1.iew.lsq.thread0.squashedStores 647934 # Number of stores squashed
|
|
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu1.iew.lsq.thread0.rescheduledLoads 17097171 # Number of loads that were rescheduled
|
|
system.cpu1.iew.lsq.thread0.cacheBlocked 3878321 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu1.iew.iewSquashCycles 388308 # Number of cycles IEW is squashing
|
|
system.cpu1.iew.iewBlockCycles 50150951 # Number of cycles IEW is blocking
|
|
system.cpu1.iew.iewUnblockCycles 3201381 # Number of cycles IEW is unblocking
|
|
system.cpu1.iew.iewDispatchedInsts 45487056 # Number of instructions dispatched to IQ
|
|
system.cpu1.iew.iewDispSquashedInsts 83691 # Number of squashed instructions skipped by dispatch
|
|
system.cpu1.iew.iewDispLoadInsts 8452340 # Number of dispatched load instructions
|
|
system.cpu1.iew.iewDispStoreInsts 6808261 # Number of dispatched store instructions
|
|
system.cpu1.iew.iewDispNonSpecInsts 746320 # Number of dispatched non-speculative instructions
|
|
system.cpu1.iew.iewIQFullEvents 150012 # Number of times the IQ has become full, causing a stall
|
|
system.cpu1.iew.iewLSQFullEvents 2969807 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu1.iew.memOrderViolationEvents 24270 # Number of memory order violations
|
|
system.cpu1.iew.predictedTakenIncorrect 165680 # Number of branches that were predicted taken incorrectly
|
|
system.cpu1.iew.predictedNotTakenIncorrect 138748 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu1.iew.branchMispredicts 304428 # Number of branch mispredicts detected at execute
|
|
system.cpu1.iew.iewExecutedInsts 62296746 # Number of executed instructions
|
|
system.cpu1.iew.iewExecLoadInsts 28474223 # Number of load instructions executed
|
|
system.cpu1.iew.iewExecSquashedInsts 369499 # Number of squashed instructions skipped in execute
|
|
system.cpu1.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu1.iew.exec_nop 134083 # number of nop insts executed
|
|
system.cpu1.iew.exec_refs 34908741 # number of memory reference insts executed
|
|
system.cpu1.iew.exec_branches 6065757 # Number of branches executed
|
|
system.cpu1.iew.exec_stores 6434518 # Number of stores executed
|
|
system.cpu1.iew.exec_rate 0.262803 # Inst execution rate
|
|
system.cpu1.iew.wb_sent 58446379 # cumulative count of insts sent to commit
|
|
system.cpu1.iew.wb_count 41282724 # cumulative count of insts written-back
|
|
system.cpu1.iew.wb_producers 23334628 # num instructions producing a value
|
|
system.cpu1.iew.wb_consumers 41837805 # num instructions consuming a value
|
|
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu1.iew.wb_rate 0.174154 # insts written-back per cycle
|
|
system.cpu1.iew.wb_fanout 0.557740 # average fanout of values written-back
|
|
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu1.commit.commitSquashedInsts 7166738 # The number of squashed insts skipped by commit
|
|
system.cpu1.commit.commitNonSpecStalls 763265 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu1.commit.branchMispredicts 256189 # The number of times a branch was mispredicted
|
|
system.cpu1.commit.committed_per_cycle::samples 234203986 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::mean 0.162086 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::stdev 0.884581 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::0 220778060 94.27% 94.27% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::1 6743716 2.88% 97.15% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::2 1772623 0.76% 97.90% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::3 1087484 0.46% 98.37% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::4 731864 0.31% 98.68% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::5 647370 0.28% 98.96% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::6 507514 0.22% 99.17% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::7 282341 0.12% 99.29% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::8 1653014 0.71% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::total 234203986 # Number of insts commited each cycle
|
|
system.cpu1.commit.committedInsts 31407169 # Number of instructions committed
|
|
system.cpu1.commit.committedOps 37961303 # Number of ops (including micro ops) committed
|
|
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu1.commit.refs 13153120 # Number of memory references committed
|
|
system.cpu1.commit.loads 6992793 # Number of loads committed
|
|
system.cpu1.commit.membars 210663 # Number of memory barriers committed
|
|
system.cpu1.commit.branches 5351172 # Number of branches committed
|
|
system.cpu1.commit.fp_insts 5118 # Number of committed floating point instructions.
|
|
system.cpu1.commit.int_insts 33489601 # Number of committed integer instructions.
|
|
system.cpu1.commit.function_calls 519360 # Number of function calls committed.
|
|
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IntAlu 24763487 65.23% 65.23% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IntMult 43483 0.11% 65.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatMisc 1213 0.00% 65.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::MemRead 6992793 18.42% 83.77% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::MemWrite 6160327 16.23% 100.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::total 37961303 # Class of committed instruction
|
|
system.cpu1.commit.bw_lim_events 1653014 # number cycles where commit BW limit reached
|
|
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu1.rob.rob_reads 276729293 # The number of ROB reads
|
|
system.cpu1.rob.rob_writes 91408516 # The number of ROB writes
|
|
system.cpu1.timesIdled 270232 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu1.idleCycles 1652965 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu1.quiesceCycles 2279190242 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu1.committedInsts 31323407 # Number of Instructions Simulated
|
|
system.cpu1.committedOps 37877541 # Number of Ops (including micro ops) Simulated
|
|
system.cpu1.cpi 7.567726 # CPI: Cycles Per Instruction
|
|
system.cpu1.cpi_total 7.567726 # CPI: Total CPI of All Threads
|
|
system.cpu1.ipc 0.132140 # IPC: Instructions Per Cycle
|
|
system.cpu1.ipc_total 0.132140 # IPC: Total IPC of All Threads
|
|
system.cpu1.int_regfile_reads 71111518 # number of integer regfile reads
|
|
system.cpu1.int_regfile_writes 26004877 # number of integer regfile writes
|
|
system.cpu1.fp_regfile_reads 44415 # number of floating regfile reads
|
|
system.cpu1.fp_regfile_writes 42120 # number of floating regfile writes
|
|
system.cpu1.cc_regfile_reads 209232786 # number of cc regfile reads
|
|
system.cpu1.cc_regfile_writes 17062784 # number of cc regfile writes
|
|
system.cpu1.misc_regfile_reads 298304880 # number of misc regfile reads
|
|
system.cpu1.misc_regfile_writes 608841 # number of misc regfile writes
|
|
system.iocache.tags.replacements 0 # number of replacements
|
|
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.tag_accesses 0 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 0 # Number of data accesses
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1732753268848 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::total 1732753268848 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1732753268848 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::total 1732753268848 # number of overall MSHR uncacheable cycles
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 83356 # number of quiesce instructions executed
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
|
|
---------- End Simulation Statistics ----------
|