1106 lines
131 KiB
Text
1106 lines
131 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.616536 # Number of seconds simulated
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sim_ticks 2616536215000 # Number of ticks simulated
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final_tick 2616536215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 594955 # Simulator instruction rate (inst/s)
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host_op_rate 757104 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 25859148121 # Simulator tick rate (ticks/s)
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host_mem_usage 420956 # Number of bytes of host memory used
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host_seconds 101.18 # Real time elapsed on the host
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sim_insts 60200059 # Number of instructions simulated
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sim_ops 76606878 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.inst 703944 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9089816 # Number of bytes read from this memory
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system.physmem.bytes_read::total 132477600 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 703944 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 703944 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 3706240 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
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system.physmem.bytes_written::total 6722312 # Number of bytes written to this memory
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system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.inst 17211 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 142064 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 15494706 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 57910 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 811928 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.clcd 46887710 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.inst 269037 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 3473988 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 50630906 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 269037 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 269037 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1416468 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 1152696 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2569165 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1416468 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.clcd 46887710 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 269037 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 4626685 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 53200071 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 15494706 # Number of read requests accepted
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system.physmem.writeReqs 811928 # Number of write requests accepted
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system.physmem.readBursts 15494706 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 811928 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 991531648 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 129536 # Total number of bytes read from write queue
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system.physmem.bytesWritten 6740736 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 132477600 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 6722312 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 2024 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 706583 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 4515 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 967775 # Per bank write bursts
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system.physmem.perBankRdBursts::1 967715 # Per bank write bursts
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system.physmem.perBankRdBursts::2 967672 # Per bank write bursts
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system.physmem.perBankRdBursts::3 967748 # Per bank write bursts
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system.physmem.perBankRdBursts::4 974561 # Per bank write bursts
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system.physmem.perBankRdBursts::5 968173 # Per bank write bursts
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system.physmem.perBankRdBursts::6 967769 # Per bank write bursts
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system.physmem.perBankRdBursts::7 967703 # Per bank write bursts
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system.physmem.perBankRdBursts::8 968545 # Per bank write bursts
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system.physmem.perBankRdBursts::9 968137 # Per bank write bursts
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system.physmem.perBankRdBursts::10 967949 # Per bank write bursts
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system.physmem.perBankRdBursts::11 967746 # Per bank write bursts
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system.physmem.perBankRdBursts::12 967851 # Per bank write bursts
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system.physmem.perBankRdBursts::13 967741 # Per bank write bursts
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system.physmem.perBankRdBursts::14 967800 # Per bank write bursts
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system.physmem.perBankRdBursts::15 967797 # Per bank write bursts
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system.physmem.perBankWrBursts::0 6510 # Per bank write bursts
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system.physmem.perBankWrBursts::1 6313 # Per bank write bursts
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system.physmem.perBankWrBursts::2 6323 # Per bank write bursts
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system.physmem.perBankWrBursts::3 6241 # Per bank write bursts
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system.physmem.perBankWrBursts::4 6804 # Per bank write bursts
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system.physmem.perBankWrBursts::5 6995 # Per bank write bursts
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system.physmem.perBankWrBursts::6 6800 # Per bank write bursts
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system.physmem.perBankWrBursts::7 6791 # Per bank write bursts
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system.physmem.perBankWrBursts::8 7084 # Per bank write bursts
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system.physmem.perBankWrBursts::9 6747 # Per bank write bursts
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system.physmem.perBankWrBursts::10 6568 # Per bank write bursts
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system.physmem.perBankWrBursts::11 6457 # Per bank write bursts
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system.physmem.perBankWrBursts::12 6495 # Per bank write bursts
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system.physmem.perBankWrBursts::13 6295 # Per bank write bursts
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system.physmem.perBankWrBursts::14 6428 # Per bank write bursts
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system.physmem.perBankWrBursts::15 6473 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 2616531854000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 6664 # Read request sizes (log2)
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system.physmem.readPktSize::3 15335424 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 152618 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 754018 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 57910 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 1116573 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 960474 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 961347 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 975907 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 963056 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 965451 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 2812276 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 2805674 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 3709925 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 42008 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 34639 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 36264 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 33338 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 31474 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 22310 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 21858 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 108 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 2478 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 2541 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 3152 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 4807 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 4792 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 4786 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 4793 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 4827 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 4839 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 4834 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 5981 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 4975 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 4962 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 5804 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 4869 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 4878 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 4878 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 4793 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 1099 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 1078 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 1070 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 1076 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 1063 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 1063 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 1060 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 1060 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 1060 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 1060 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 1060 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 1060 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 1060 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 1060 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 1060 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 1059 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 1059 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 1059 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 1059 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 1058 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 1058 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 977394 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 1014.625651 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 1002.644045 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 87.222028 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 3543 0.36% 0.36% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 3286 0.34% 0.70% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 1787 0.18% 0.88% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 1165 0.12% 1.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 902 0.09% 1.09% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 711 0.07% 1.17% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 580 0.06% 1.23% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 432 0.04% 1.27% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 964988 98.73% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 977394 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 4784 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 3238.435619 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 134294.504205 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-524287 4779 99.90% 99.90% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::524288-1.04858e+06 3 0.06% 99.96% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 1 0.02% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::8.9129e+06-9.43718e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 4784 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 4784 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 22.015886 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 20.524536 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 9.242033 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16 2224 46.49% 46.49% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::17 36 0.75% 47.24% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::18 227 4.74% 51.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::19 1224 25.59% 77.57% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20 8 0.17% 77.74% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::21 4 0.08% 77.82% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::23 1 0.02% 77.84% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::33 1 0.02% 77.86% # Writes before turning the bus around for reads
|
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system.physmem.wrPerTurnAround::34 1 0.02% 77.88% # Writes before turning the bus around for reads
|
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system.physmem.wrPerTurnAround::39 945 19.75% 97.64% # Writes before turning the bus around for reads
|
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system.physmem.wrPerTurnAround::40 67 1.40% 99.04% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::41 15 0.31% 99.35% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::42 31 0.65% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 4784 # Writes before turning the bus around for reads
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system.physmem.totQLat 588095657500 # Total ticks spent queuing
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system.physmem.totMemAccLat 694960871250 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 77463410000 # Total ticks spent in databus transfers
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system.physmem.totBankLat 29401803750 # Total ticks spent accessing banks
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system.physmem.avgQLat 37959.58 # Average queueing delay per DRAM burst
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system.physmem.avgBankLat 1897.79 # Average bank access latency per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 44857.36 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 378.95 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 2.58 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 50.63 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 2.57 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 2.98 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 2.96 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 7.03 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 29.46 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 14490606 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 90101 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 93.53 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 85.53 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 160458.12 # Average gap between requests
|
|
system.physmem.pageHitRate 93.48 # Row buffer hit rate, read and write combined
|
|
system.physmem.prechargeAllPercent 3.85 # Percentage of time for which DRAM has all the banks in precharge state
|
|
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
|
|
system.membus.throughput 54116651 # Throughput (bytes/s)
|
|
system.membus.trans_dist::ReadReq 16546597 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 16546597 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 763385 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 763385 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 57910 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 4515 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 4515 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 132217 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 132217 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383088 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893540 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280490 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 34951338 # Packet count per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390542 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516520 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914786 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::total 141598178 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.data_through_bus 141598178 # Total data (bytes)
|
|
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.membus.reqLayer0.occupancy 1206225000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 3615000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer6.occupancy 17911294000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 4951349139 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 38238689000 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 1.5 # Layer utilization (%)
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
|
system.iobus.throughput 47801339 # Throughput (bytes/s)
|
|
system.iobus.trans_dist::ReadReq 16518785 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 16518785 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 8183 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 8183 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 2383088 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 33053936 # Packet count per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::total 2390542 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::total 125073934 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.data_through_bus 125073934 # Total data (bytes)
|
|
system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 534000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 2374905000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 38265059000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 14996179 # DTB read hits
|
|
system.cpu.dtb.read_misses 7337 # DTB read misses
|
|
system.cpu.dtb.write_hits 11230334 # DTB write hits
|
|
system.cpu.dtb.write_misses 2213 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 3411 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 15003516 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 11232547 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 26226513 # DTB hits
|
|
system.cpu.dtb.misses 9550 # DTB misses
|
|
system.cpu.dtb.accesses 26236063 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.inst_hits 61493932 # ITB inst hits
|
|
system.cpu.itb.inst_misses 4471 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 2370 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 61498403 # ITB inst accesses
|
|
system.cpu.itb.hits 61493932 # DTB hits
|
|
system.cpu.itb.misses 4471 # DTB misses
|
|
system.cpu.itb.accesses 61498403 # DTB accesses
|
|
system.cpu.numCycles 5233072430 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 60200059 # Number of instructions committed
|
|
system.cpu.committedOps 76606878 # Number of ops (including micro ops) committed
|
|
system.cpu.num_int_alu_accesses 69208659 # Number of integer alu accesses
|
|
system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
|
|
system.cpu.num_func_calls 2140468 # number of times a function call or return occured
|
|
system.cpu.num_conditional_control_insts 7948676 # number of instructions that are conditional controls
|
|
system.cpu.num_int_insts 69208659 # number of integer instructions
|
|
system.cpu.num_fp_insts 10269 # number of float instructions
|
|
system.cpu.num_int_register_reads 401368432 # number of times the integer registers were read
|
|
system.cpu.num_int_register_writes 74518953 # number of times the integer registers were written
|
|
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
|
|
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
|
|
system.cpu.num_mem_refs 27394027 # number of memory refs
|
|
system.cpu.num_load_insts 15660244 # Number of load instructions
|
|
system.cpu.num_store_insts 11733783 # Number of store instructions
|
|
system.cpu.num_idle_cycles 4581664281.608249 # Number of idle cycles
|
|
system.cpu.num_busy_cycles 651408148.391751 # Number of busy cycles
|
|
system.cpu.not_idle_fraction 0.124479 # Percentage of non-idle cycles
|
|
system.cpu.idle_fraction 0.875521 # Percentage of idle cycles
|
|
system.cpu.Branches 10308791 # Number of branches fetched
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 83016 # number of quiesce instructions executed
|
|
system.cpu.icache.tags.replacements 856277 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 510.865256 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 60637143 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 856789 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 70.772551 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 20019652250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 510.865256 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.997784 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.997784 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 267 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 62350721 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 62350721 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 60637143 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 60637143 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 60637143 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 60637143 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 60637143 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 60637143 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 856789 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 856789 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 856789 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 856789 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 856789 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 856789 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 11768796500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 11768796500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 11768796500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 11768796500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 11768796500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 11768796500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 61493932 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 61493932 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 61493932 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 61493932 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 61493932 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 61493932 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013933 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.013933 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.013933 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.013933 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.013933 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.013933 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13735.933234 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 13735.933234 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13735.933234 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 13735.933234 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13735.933234 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 13735.933234 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856789 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 856789 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 856789 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 856789 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 856789 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 856789 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10051259500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 10051259500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10051259500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 10051259500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10051259500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 10051259500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 442799750 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 442799750 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 442799750 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::total 442799750 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013933 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.013933 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.013933 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11731.312494 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11731.312494 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11731.312494 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 11731.312494 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11731.312494 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 11731.312494 # average overall mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 62510 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 50754.341814 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 1682268 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 127892 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 13.153817 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 2565667436000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 37718.224228 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884316 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000703 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 6993.295627 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 6038.936941 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.575534 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106709 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.092147 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.774450 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65378 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2162 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6903 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56263 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997589 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 17138143 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 17138143 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8709 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3533 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 844568 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 369661 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 1226471 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 595273 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 595273 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 113398 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 113398 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 8709 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.itb.walker 3533 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 844568 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 483059 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 1339869 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.dtb.walker 8709 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.itb.walker 3533 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 844568 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 483059 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 1339869 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 10585 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 9809 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 20401 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2905 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 2905 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 133827 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 133827 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 10585 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 143636 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 154228 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 10585 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 143636 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 154228 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 397250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 150000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 747154500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 739313250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 1487015000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 469980 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 469980 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9526600640 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 9526600640 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 397250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 150000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 747154500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 10265913890 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 11013615640 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 397250 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 150000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 747154500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 10265913890 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 11013615640 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8714 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3535 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 855153 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 379470 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 1246872 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 595273 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 595273 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2931 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 2931 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247225 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 247225 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8714 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3535 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 855153 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 626695 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 1494097 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8714 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3535 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 855153 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 626695 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 1494097 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000574 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000566 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012378 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025849 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.016362 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991129 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991129 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541317 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.541317 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000574 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000566 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012378 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.229196 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.103225 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000574 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000566 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012378 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.229196 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.103225 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 79450 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 75000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70586.159660 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75370.909369 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 72889.319151 # average ReadReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 161.783133 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 161.783133 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71185.938861 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71185.938861 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 79450 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70586.159660 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71471.733340 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 71411.258915 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 79450 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70586.159660 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71471.733340 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 71411.258915 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 57910 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 57910 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10585 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9809 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 20401 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2905 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2905 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133827 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 133827 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 10585 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 143636 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 154228 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 10585 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 143636 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 154228 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 335750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 614626500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 616437250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1231524500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29056905 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29056905 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7852026860 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7852026860 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 335750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 614626500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8468464110 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 9083551360 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 335750 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 614626500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8468464110 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 9083551360 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 351469750 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166664489250 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167015959000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16706272596 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16706272596 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 351469750 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183370761846 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183722231596 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025849 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016362 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991129 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991129 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541317 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541317 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229196 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.103225 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229196 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.103225 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67150 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58065.800661 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62844.046284 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60365.888927 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.376936 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.376936 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58672.964798 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58672.964798 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67150 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58065.800661 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58957.810786 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58896.901730 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67150 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58065.800661 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58957.810786 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58896.901730 # average overall mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 626183 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.875243 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 23656065 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 626695 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 37.747333 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 671680250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.875243 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999756 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999756 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 97757735 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 97757735 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 13196205 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 13196205 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 9972754 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 9972754 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 236397 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 236397 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 247778 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 247778 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 23168959 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 23168959 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 23168959 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 23168959 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 368088 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 368088 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 250156 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 250156 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 11382 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 11382 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 618244 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 618244 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 618244 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 618244 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5418733500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 5418733500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 11526229765 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 11526229765 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 157891250 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 157891250 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 16944963265 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 16944963265 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 16944963265 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 16944963265 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 13564293 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 13564293 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 10222910 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 10222910 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247779 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 247779 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247778 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 247778 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 23787203 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 23787203 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 23787203 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 23787203 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027137 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.027137 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024470 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.024470 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045936 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045936 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.025991 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.025991 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.025991 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.025991 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14721.298983 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 14721.298983 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46076.167531 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 46076.167531 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13872.012827 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13872.012827 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 27408.213044 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 27408.213044 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 27408.213044 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 27408.213044 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 595273 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 595273 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368088 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 368088 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250156 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 250156 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11382 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 11382 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 618244 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 618244 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 618244 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 618244 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4680319500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4680319500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10976351235 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10976351235 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135073750 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135073750 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15656670735 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 15656670735 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15656670735 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 15656670735 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182058625250 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182058625250 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26242395404 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26242395404 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208301020654 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 208301020654 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027137 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027137 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024470 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024470 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045936 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045936 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025991 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.025991 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025991 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.025991 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12715.218915 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12715.218915 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43878.025052 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43878.025052 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11867.312423 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11867.312423 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25324.420027 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25324.420027 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25324.420027 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 25324.420027 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.throughput 52967752 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 2454681 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 2454681 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 763385 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 763385 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 595273 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 2931 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 2931 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 247225 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 247225 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725204 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749577 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12461 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27438 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 7514680 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54756316 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83620422 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14140 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34856 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 138425734 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 138425734 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 166308 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 3008713250 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1295332250 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 2533285861 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer3.occupancy 18724250 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 0 # number of replacements
|
|
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.tag_accesses 0 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 0 # Number of data accesses
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1763840630000 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::total 1763840630000 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1763840630000 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::total 1763840630000 # number of overall MSHR uncacheable cycles
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|