Andreas Sandberg b904bd5437 sim: Add a system-global option to bypass caches ... Virtualized CPUs and the fastmem mode of the atomic CPU require direct access to physical memory. We currently require caches to be disabled when using them to prevent chaos. This is not ideal when switching between hardware virutalized CPUs and other CPU models as it would require a configuration change on each switch. This changeset introduces a new version of the atomic memory mode, 'atomic_noncaching', where memory accesses are inserted into the memory system as atomic accesses, but bypass caches. To make memory mode tests cleaner, the following methods are added to the System class: * isAtomicMode() -- True if the memory mode is 'atomic' or 'direct'. * isTimingMode() -- True if the memory mode is 'timing'. * bypassCaches() -- True if caches should be bypassed. The old getMemoryMode() and setMemoryMode() methods should never be used from the C++ world anymore.		2013-02-15 17:40:09 -05:00
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SConscript	cpu: Add support for protobuf input for the trace generator	2013-01-07 13:05:37 -05:00
traffic_gen.cc	sim: Add a system-global option to bypass caches	2013-02-15 17:40:09 -05:00
traffic_gen.hh	cpu: Share the send functionality between traffic generators	2013-01-07 13:05:37 -05:00
TrafficGen.py	sim: Include object header files in SWIG interfaces	2012-11-02 11:32:01 -05:00