Mostly just config.ini updates, though the different response latency for bad addresses caused very minor timing changes in the O3 Linux boot tests.
239 lines
26 KiB
Text
239 lines
26 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 2784324 # Simulator instruction rate (inst/s)
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host_mem_usage 208188 # Number of bytes of host memory used
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host_seconds 33.01 # Real time elapsed on the host
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host_tick_rate 3597581254 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 91903056 # Number of instructions simulated
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sim_seconds 0.118747 # Number of seconds simulated
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sim_ticks 118747246000 # Number of ticks simulated
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system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 51313.684211 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48313.684211 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 24374000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 22949000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 6499244 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 104104000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 1859 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 98527000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 1859 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 55046.272494 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 52046.272494 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 26494967 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 128478000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.000088 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 2334 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 121476000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 2334 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 55046.272494 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 52046.272494 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 26494967 # number of overall hits
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system.cpu.dcache.overall_miss_latency 128478000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.000088 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 2334 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 121476000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 2334 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 157 # number of replacements
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system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 1442.022508 # Cycle average of tags in use
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system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 104 # number of writebacks
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system.cpu.dtb.data_accesses 26497334 # DTB accesses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_hits 26497301 # DTB hits
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system.cpu.dtb.data_misses 33 # DTB misses
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.read_accesses 19996208 # DTB read accesses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_hits 19996198 # DTB read hits
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system.cpu.dtb.read_misses 10 # DTB read misses
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system.cpu.dtb.write_accesses 6501126 # DTB write accesses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_hits 6501103 # DTB write hits
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system.cpu.dtb.write_misses 23 # DTB write misses
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system.cpu.icache.ReadReq_accesses 91903090 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 26935.605170 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 23935.605170 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 91894580 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 229222000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 203692000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 91903090 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 26935.605170 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency
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system.cpu.icache.demand_hits 91894580 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 229222000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses
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system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 203692000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 91894580 # number of overall hits
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system.cpu.icache.overall_miss_latency 229222000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses
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system.cpu.icache.overall_misses 8510 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 203692000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 6681 # number of replacements
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system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 1418.025998 # Cycle average of tags in use
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system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.fetch_accesses 91903137 # ITB accesses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_hits 91903090 # ITB hits
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system.cpu.itb.fetch_misses 47 # ITB misses
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadExReq_miss_latency 90896000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_misses 1748 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 69920000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadReq_accesses 8985 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_hits 5942 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_miss_latency 158236000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_rate 0.338676 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_misses 3043 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency 121720000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338676 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_misses 3043 # number of ReadReq MSHR misses
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system.cpu.l2cache.UpgradeReq_accesses 111 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.UpgradeReq_miss_latency 5772000 # number of UpgradeReq miss cycles
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system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_misses 111 # number of UpgradeReq misses
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system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4440000 # number of UpgradeReq MSHR miss cycles
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_mshr_misses 111 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits
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system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.l2cache.avg_refs 1.969435 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.demand_accesses 10733 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.demand_hits 5942 # number of demand (read+write) hits
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system.cpu.l2cache.demand_miss_latency 249132000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_rate 0.446380 # miss rate for demand accesses
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system.cpu.l2cache.demand_misses 4791 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.demand_mshr_miss_latency 191640000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_rate 0.446380 # mshr miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_misses 4791 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.overall_accesses 10733 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_hits 5942 # number of overall hits
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system.cpu.l2cache.overall_miss_latency 249132000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_rate 0.446380 # miss rate for overall accesses
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system.cpu.l2cache.overall_misses 4791 # number of overall misses
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.l2cache.overall_mshr_miss_latency 191640000 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_rate 0.446380 # mshr miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_misses 4791 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.l2cache.replacements 0 # number of replacements
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system.cpu.l2cache.sampled_refs 3010 # Sample count of references to valid blocks.
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.l2cache.tagsinuse 2022.059349 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 5928 # Total number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.writebacks 0 # number of writebacks
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 237494492 # number of cpu cycles simulated
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system.cpu.num_insts 91903056 # Number of instructions executed
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system.cpu.num_refs 26537141 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
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---------- End Simulation Statistics ----------
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