c8cf71f1a0
This patch adds a method to the Wavefront class to compute the actual workgroup size. This can be different from the maximum workgroup size specified when launching the kernel through the NDRange object. Current solution is still not optimal, as we are computing these for each wavefront and the dispatcher also needs to have this information and can't actually call Wavefront::computeActuallWgSz before the wavefronts are being created. A long term solution would be to have a Workgroup class that deals with all these details.
750 lines
24 KiB
C++
750 lines
24 KiB
C++
/*
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* Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: John Kalamatianos, Anthony Gutierrez
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*/
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#ifndef __COMPUTE_UNIT_HH__
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#define __COMPUTE_UNIT_HH__
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#include <deque>
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#include <map>
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#include <unordered_map>
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#include <vector>
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#include "base/callback.hh"
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#include "base/statistics.hh"
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#include "base/types.hh"
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#include "enums/PrefetchType.hh"
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#include "gpu-compute/exec_stage.hh"
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#include "gpu-compute/fetch_stage.hh"
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#include "gpu-compute/global_memory_pipeline.hh"
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#include "gpu-compute/local_memory_pipeline.hh"
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#include "gpu-compute/qstruct.hh"
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#include "gpu-compute/schedule_stage.hh"
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#include "gpu-compute/scoreboard_check_stage.hh"
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#include "mem/mem_object.hh"
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#include "mem/port.hh"
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static const int MAX_REGS_FOR_NON_VEC_MEM_INST = 1;
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static const int MAX_WIDTH_FOR_MEM_INST = 32;
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class NDRange;
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class Shader;
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class VectorRegisterFile;
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struct ComputeUnitParams;
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enum EXEC_POLICY
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{
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OLDEST = 0,
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RR
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};
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// List of execution units
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enum EXEC_UNIT
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{
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SIMD0 = 0,
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SIMD1,
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SIMD2,
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SIMD3,
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GLBMEM_PIPE,
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LDSMEM_PIPE,
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NUM_UNITS
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};
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enum TLB_CACHE
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{
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TLB_MISS_CACHE_MISS = 0,
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TLB_MISS_CACHE_HIT,
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TLB_HIT_CACHE_MISS,
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TLB_HIT_CACHE_HIT
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};
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class ComputeUnit : public MemObject
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{
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public:
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FetchStage fetchStage;
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ScoreboardCheckStage scoreboardCheckStage;
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ScheduleStage scheduleStage;
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ExecStage execStage;
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GlobalMemPipeline globalMemoryPipe;
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LocalMemPipeline localMemoryPipe;
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// Buffers used to communicate between various pipeline stages
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// List of waves which are ready to be scheduled.
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// Each execution resource has a ready list. readyList is
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// used to communicate between scoreboardCheck stage and
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// schedule stage
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// TODO: make enum to index readyList
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std::vector<std::vector<Wavefront*>> readyList;
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// Stores the status of waves. A READY implies the
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// wave is ready to be scheduled this cycle and
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// is already present in the readyList. waveStatusList is
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// used to communicate between scoreboardCheck stage and
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// schedule stage
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// TODO: convert std::pair to a class to increase readability
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std::vector<std::vector<std::pair<Wavefront*, WAVE_STATUS>>> waveStatusList;
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// List of waves which will be dispatched to
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// each execution resource. A FILLED implies
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// dispatch list is non-empty and
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// execution unit has something to execute
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// this cycle. Currently, the dispatch list of
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// an execution resource can hold only one wave because
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// an execution resource can execute only one wave in a cycle.
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// dispatchList is used to communicate between schedule
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// and exec stage
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// TODO: convert std::pair to a class to increase readability
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std::vector<std::pair<Wavefront*, DISPATCH_STATUS>> dispatchList;
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int rrNextMemID; // used by RR WF exec policy to cycle through WF's
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int rrNextALUWp;
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typedef ComputeUnitParams Params;
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std::vector<std::vector<Wavefront*>> wfList;
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int cu_id;
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// array of vector register files, one per SIMD
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std::vector<VectorRegisterFile*> vrf;
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// Number of vector ALU units (SIMDs) in CU
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int numSIMDs;
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// number of pipe stages for bypassing data to next dependent single
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// precision vector instruction inside the vector ALU pipeline
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int spBypassPipeLength;
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// number of pipe stages for bypassing data to next dependent double
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// precision vector instruction inside the vector ALU pipeline
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int dpBypassPipeLength;
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// number of cycles per issue period
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int issuePeriod;
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// Number of global and local memory execution resources in CU
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int numGlbMemUnits;
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int numLocMemUnits;
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// tracks the last cycle a vector instruction was executed on a SIMD
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std::vector<uint64_t> lastExecCycle;
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// true if we allow a separate TLB per lane
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bool perLaneTLB;
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// if 0, TLB prefetching is off.
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int prefetchDepth;
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// if fixed-stride prefetching, this is the stride.
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int prefetchStride;
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std::vector<Addr> lastVaddrCU;
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std::vector<std::vector<Addr>> lastVaddrSimd;
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std::vector<std::vector<std::vector<Addr>>> lastVaddrWF;
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Enums::PrefetchType prefetchType;
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EXEC_POLICY exec_policy;
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bool xact_cas_mode;
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bool debugSegFault;
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bool functionalTLB;
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bool localMemBarrier;
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/*
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* for Counting page accesses
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*
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* cuExitCallback inherits from Callback. When you register a callback
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* function as an exit callback, it will get added to an exit callback
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* queue, such that on simulation exit, all callbacks in the callback
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* queue will have their process() function called.
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*/
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bool countPages;
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Shader *shader;
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uint32_t barrier_id;
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// vector of Vector ALU (MACC) pipelines
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std::vector<WaitClass> aluPipe;
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// minimum issue period per SIMD unit (in cycles)
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std::vector<WaitClass> wfWait;
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// Resource control for Vector Register File->Global Memory pipe buses
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std::vector<WaitClass> vrfToGlobalMemPipeBus;
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// Resource control for Vector Register File->Local Memory pipe buses
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std::vector<WaitClass> vrfToLocalMemPipeBus;
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int nextGlbMemBus;
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int nextLocMemBus;
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// Resource control for global memory to VRF data/address bus
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WaitClass glbMemToVrfBus;
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// Resource control for local memory to VRF data/address bus
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WaitClass locMemToVrfBus;
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uint32_t vrfToCoalescerBusWidth; // VRF->Coalescer data bus width in bytes
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uint32_t coalescerToVrfBusWidth; // Coalescer->VRF data bus width in bytes
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uint32_t numCyclesPerStoreTransfer; // number of cycles per vector store
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uint32_t numCyclesPerLoadTransfer; // number of cycles per vector load
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Tick req_tick_latency;
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Tick resp_tick_latency;
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// number of vector registers being reserved for each SIMD unit
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std::vector<int> vectorRegsReserved;
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// number of vector registers per SIMD unit
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uint32_t numVecRegsPerSimd;
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// Support for scheduling VGPR status update events
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std::vector<std::pair<uint32_t, uint32_t> > regIdxVec;
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std::vector<uint64_t> timestampVec;
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std::vector<uint8_t> statusVec;
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void
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registerEvent(uint32_t simdId,
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uint32_t regIdx,
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uint32_t operandSize,
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uint64_t when,
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uint8_t newStatus) {
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regIdxVec.push_back(std::make_pair(simdId, regIdx));
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timestampVec.push_back(when);
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statusVec.push_back(newStatus);
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if (operandSize > 4) {
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regIdxVec.push_back(std::make_pair(simdId,
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((regIdx + 1) %
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numVecRegsPerSimd)));
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timestampVec.push_back(when);
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statusVec.push_back(newStatus);
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}
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}
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void updateEvents();
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// this hash map will keep track of page divergence
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// per memory instruction per wavefront. The hash map
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// is cleared in GPUDynInst::updateStats() in gpu_dyn_inst.cc.
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std::map<Addr, int> pagesTouched;
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ComputeUnit(const Params *p);
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~ComputeUnit();
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int spBypassLength() { return spBypassPipeLength; };
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int dpBypassLength() { return dpBypassPipeLength; };
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int storeBusLength() { return numCyclesPerStoreTransfer; };
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int loadBusLength() { return numCyclesPerLoadTransfer; };
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int wfSize() const { return wavefrontSize; };
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void resizeRegFiles(int num_cregs, int num_sregs, int num_dregs);
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void exec();
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void initiateFetch(Wavefront *wavefront);
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void fetch(PacketPtr pkt, Wavefront *wavefront);
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void fillKernelState(Wavefront *w, NDRange *ndr);
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void startWavefront(Wavefront *w, int waveId, LdsChunk *ldsChunk,
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NDRange *ndr);
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void StartWorkgroup(NDRange *ndr);
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int ReadyWorkgroup(NDRange *ndr);
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bool isVecAlu(int unitId) { return unitId >= SIMD0 && unitId <= SIMD3; }
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bool isGlbMem(int unitId) { return unitId == GLBMEM_PIPE; }
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bool isShrMem(int unitId) { return unitId == LDSMEM_PIPE; }
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int GlbMemUnitId() { return GLBMEM_PIPE; }
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int ShrMemUnitId() { return LDSMEM_PIPE; }
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int nextGlbRdBus() { return (++nextGlbMemBus) % numGlbMemUnits; }
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int nextLocRdBus() { return (++nextLocMemBus) % numLocMemUnits; }
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/* This function cycles through all the wavefronts in all the phases to see
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* if all of the wavefronts which should be associated with one barrier
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* (denoted with _barrier_id), are all at the same barrier in the program
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* (denoted by bcnt). When the number at the barrier matches bslots, then
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* return true.
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*/
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int AllAtBarrier(uint32_t _barrier_id, uint32_t bcnt, uint32_t bslots);
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bool cedeSIMD(int simdId, int wfSlotId);
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template<typename c0, typename c1> void doSmReturn(GPUDynInstPtr gpuDynInst);
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virtual void init();
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void sendRequest(GPUDynInstPtr gpuDynInst, int index, PacketPtr pkt);
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void sendSyncRequest(GPUDynInstPtr gpuDynInst, int index, PacketPtr pkt);
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void injectGlobalMemFence(GPUDynInstPtr gpuDynInst,
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bool kernelLaunch=true,
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RequestPtr req=nullptr);
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void handleMemPacket(PacketPtr pkt, int memport_index);
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bool processTimingPacket(PacketPtr pkt);
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void processFetchReturn(PacketPtr pkt);
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void updatePageDivergenceDist(Addr addr);
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MasterID masterId() { return _masterId; }
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bool isDone() const;
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bool isSimdDone(uint32_t) const;
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protected:
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MasterID _masterId;
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LdsState &lds;
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public:
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// the following stats compute the avg. TLB accesslatency per
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// uncoalesced request (only for data)
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Stats::Scalar tlbRequests;
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Stats::Scalar tlbCycles;
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Stats::Formula tlbLatency;
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// hitsPerTLBLevel[x] are the hits in Level x TLB. x = 0 is the page table.
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Stats::Vector hitsPerTLBLevel;
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Stats::Scalar ldsBankAccesses;
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Stats::Distribution ldsBankConflictDist;
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// over all memory instructions executed over all wavefronts
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// how many touched 0-4 pages, 4-8, ..., 60-64 pages
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Stats::Distribution pageDivergenceDist;
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Stats::Scalar dynamicGMemInstrCnt;
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Stats::Scalar dynamicLMemInstrCnt;
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Stats::Scalar wgBlockedDueLdsAllocation;
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// Number of instructions executed, i.e. if 64 (or 32 or 7) lanes are active
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// when the instruction is committed, this number is still incremented by 1
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Stats::Scalar numInstrExecuted;
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// Number of cycles among successive instruction executions across all
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// wavefronts of the same CU
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Stats::Distribution execRateDist;
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// number of individual vector operations executed
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Stats::Scalar numVecOpsExecuted;
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// Total cycles that something is running on the GPU
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Stats::Scalar totalCycles;
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Stats::Formula vpc; // vector ops per cycle
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Stats::Formula ipc; // vector instructions per cycle
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Stats::Distribution controlFlowDivergenceDist;
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Stats::Distribution activeLanesPerGMemInstrDist;
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Stats::Distribution activeLanesPerLMemInstrDist;
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// number of vector ALU instructions received
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Stats::Formula numALUInstsExecuted;
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// number of times a WG can not start due to lack of free VGPRs in SIMDs
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Stats::Scalar numTimesWgBlockedDueVgprAlloc;
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Stats::Scalar numCASOps;
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Stats::Scalar numFailedCASOps;
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Stats::Scalar completedWfs;
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// flag per vector SIMD unit that is set when there is at least one
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// WV that has a vector ALU instruction as the oldest in its
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// Instruction Buffer: Defined in the Scoreboard stage, consumed
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// by the Execute stage.
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std::vector<bool> vectorAluInstAvail;
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// number of available (oldest) LDS instructions that could have
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// been issued to the LDS at a specific issue slot
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int shrMemInstAvail;
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// number of available Global memory instructions that could have
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// been issued to TCP at a specific issue slot
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int glbMemInstAvail;
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void
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regStats();
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LdsState &
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getLds() const
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{
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return lds;
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}
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int32_t
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getRefCounter(const uint32_t dispatchId, const uint32_t wgId) const;
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bool
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sendToLds(GPUDynInstPtr gpuDynInst) __attribute__((warn_unused_result));
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typedef std::unordered_map<Addr, std::pair<int, int>> pageDataStruct;
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pageDataStruct pageAccesses;
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class CUExitCallback : public Callback
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{
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private:
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ComputeUnit *computeUnit;
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public:
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virtual ~CUExitCallback() { }
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CUExitCallback(ComputeUnit *_cu)
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{
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computeUnit = _cu;
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}
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virtual void
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process();
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};
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CUExitCallback *cuExitCallback;
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/** Data access Port **/
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class DataPort : public MasterPort
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{
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public:
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DataPort(const std::string &_name, ComputeUnit *_cu, PortID _index)
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: MasterPort(_name, _cu), computeUnit(_cu),
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index(_index) { }
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bool snoopRangeSent;
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struct SenderState : public Packet::SenderState
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{
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GPUDynInstPtr _gpuDynInst;
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int port_index;
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Packet::SenderState *saved;
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SenderState(GPUDynInstPtr gpuDynInst, PortID _port_index,
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Packet::SenderState *sender_state=nullptr)
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: _gpuDynInst(gpuDynInst),
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port_index(_port_index),
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saved(sender_state) { }
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};
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class MemReqEvent : public Event
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{
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private:
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DataPort *dataPort;
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PacketPtr pkt;
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public:
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MemReqEvent(DataPort *_data_port, PacketPtr _pkt)
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: Event(), dataPort(_data_port), pkt(_pkt)
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{
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setFlags(Event::AutoDelete);
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}
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void process();
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const char *description() const;
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};
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class MemRespEvent : public Event
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{
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private:
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DataPort *dataPort;
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PacketPtr pkt;
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public:
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MemRespEvent(DataPort *_data_port, PacketPtr _pkt)
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: Event(), dataPort(_data_port), pkt(_pkt)
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{
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setFlags(Event::AutoDelete);
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}
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void process();
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const char *description() const;
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};
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std::deque<std::pair<PacketPtr, GPUDynInstPtr>> retries;
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protected:
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ComputeUnit *computeUnit;
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int index;
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virtual bool recvTimingResp(PacketPtr pkt);
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virtual Tick recvAtomic(PacketPtr pkt) { return 0; }
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virtual void recvFunctional(PacketPtr pkt) { }
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virtual void recvRangeChange() { }
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virtual void recvReqRetry();
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virtual void
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getDeviceAddressRanges(AddrRangeList &resp, bool &snoop)
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{
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resp.clear();
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snoop = true;
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}
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};
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// Instruction cache access port
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class SQCPort : public MasterPort
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{
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public:
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SQCPort(const std::string &_name, ComputeUnit *_cu, PortID _index)
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: MasterPort(_name, _cu), computeUnit(_cu),
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index(_index) { }
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bool snoopRangeSent;
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struct SenderState : public Packet::SenderState
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{
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Wavefront *wavefront;
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Packet::SenderState *saved;
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SenderState(Wavefront *_wavefront, Packet::SenderState
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*sender_state=nullptr)
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: wavefront(_wavefront), saved(sender_state) { }
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};
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std::deque<std::pair<PacketPtr, Wavefront*>> retries;
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protected:
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ComputeUnit *computeUnit;
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int index;
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virtual bool recvTimingResp(PacketPtr pkt);
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virtual Tick recvAtomic(PacketPtr pkt) { return 0; }
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virtual void recvFunctional(PacketPtr pkt) { }
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virtual void recvRangeChange() { }
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virtual void recvReqRetry();
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virtual void
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getDeviceAddressRanges(AddrRangeList &resp, bool &snoop)
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{
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resp.clear();
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snoop = true;
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|
}
|
|
};
|
|
|
|
/** Data TLB port **/
|
|
class DTLBPort : public MasterPort
|
|
{
|
|
public:
|
|
DTLBPort(const std::string &_name, ComputeUnit *_cu, PortID _index)
|
|
: MasterPort(_name, _cu), computeUnit(_cu),
|
|
index(_index), stalled(false)
|
|
{ }
|
|
|
|
bool isStalled() { return stalled; }
|
|
void stallPort() { stalled = true; }
|
|
void unstallPort() { stalled = false; }
|
|
|
|
/**
|
|
* here we queue all the translation requests that were
|
|
* not successfully sent.
|
|
*/
|
|
std::deque<PacketPtr> retries;
|
|
|
|
/** SenderState is information carried along with the packet
|
|
* throughout the TLB hierarchy
|
|
*/
|
|
struct SenderState: public Packet::SenderState
|
|
{
|
|
// the memInst that this is associated with
|
|
GPUDynInstPtr _gpuDynInst;
|
|
|
|
// the lane in the memInst this is associated with, so we send
|
|
// the memory request down the right port
|
|
int portIndex;
|
|
|
|
// constructor used for packets involved in timing accesses
|
|
SenderState(GPUDynInstPtr gpuDynInst, PortID port_index)
|
|
: _gpuDynInst(gpuDynInst), portIndex(port_index) { }
|
|
|
|
};
|
|
|
|
protected:
|
|
ComputeUnit *computeUnit;
|
|
int index;
|
|
bool stalled;
|
|
|
|
virtual bool recvTimingResp(PacketPtr pkt);
|
|
virtual Tick recvAtomic(PacketPtr pkt) { return 0; }
|
|
virtual void recvFunctional(PacketPtr pkt) { }
|
|
virtual void recvRangeChange() { }
|
|
virtual void recvReqRetry();
|
|
};
|
|
|
|
class ITLBPort : public MasterPort
|
|
{
|
|
public:
|
|
ITLBPort(const std::string &_name, ComputeUnit *_cu)
|
|
: MasterPort(_name, _cu), computeUnit(_cu), stalled(false) { }
|
|
|
|
|
|
bool isStalled() { return stalled; }
|
|
void stallPort() { stalled = true; }
|
|
void unstallPort() { stalled = false; }
|
|
|
|
/**
|
|
* here we queue all the translation requests that were
|
|
* not successfully sent.
|
|
*/
|
|
std::deque<PacketPtr> retries;
|
|
|
|
/** SenderState is information carried along with the packet
|
|
* throughout the TLB hierarchy
|
|
*/
|
|
struct SenderState: public Packet::SenderState
|
|
{
|
|
// The wavefront associated with this request
|
|
Wavefront *wavefront;
|
|
|
|
SenderState(Wavefront *_wavefront) : wavefront(_wavefront) { }
|
|
};
|
|
|
|
protected:
|
|
ComputeUnit *computeUnit;
|
|
bool stalled;
|
|
|
|
virtual bool recvTimingResp(PacketPtr pkt);
|
|
virtual Tick recvAtomic(PacketPtr pkt) { return 0; }
|
|
virtual void recvFunctional(PacketPtr pkt) { }
|
|
virtual void recvRangeChange() { }
|
|
virtual void recvReqRetry();
|
|
};
|
|
|
|
/**
|
|
* the port intended to communicate between the CU and its LDS
|
|
*/
|
|
class LDSPort : public MasterPort
|
|
{
|
|
public:
|
|
LDSPort(const std::string &_name, ComputeUnit *_cu, PortID _id)
|
|
: MasterPort(_name, _cu, _id), computeUnit(_cu)
|
|
{
|
|
}
|
|
|
|
bool isStalled() const { return stalled; }
|
|
void stallPort() { stalled = true; }
|
|
void unstallPort() { stalled = false; }
|
|
|
|
/**
|
|
* here we queue all the requests that were
|
|
* not successfully sent.
|
|
*/
|
|
std::queue<PacketPtr> retries;
|
|
|
|
/**
|
|
* SenderState is information carried along with the packet, esp. the
|
|
* GPUDynInstPtr
|
|
*/
|
|
class SenderState: public Packet::SenderState
|
|
{
|
|
protected:
|
|
// The actual read/write/atomic request that goes with this command
|
|
GPUDynInstPtr _gpuDynInst = nullptr;
|
|
|
|
public:
|
|
SenderState(GPUDynInstPtr gpuDynInst):
|
|
_gpuDynInst(gpuDynInst)
|
|
{
|
|
}
|
|
|
|
GPUDynInstPtr
|
|
getMemInst() const
|
|
{
|
|
return _gpuDynInst;
|
|
}
|
|
};
|
|
|
|
virtual bool
|
|
sendTimingReq(PacketPtr pkt);
|
|
|
|
protected:
|
|
|
|
bool stalled = false; ///< whether or not it is stalled
|
|
|
|
ComputeUnit *computeUnit;
|
|
|
|
virtual bool
|
|
recvTimingResp(PacketPtr pkt);
|
|
|
|
virtual Tick
|
|
recvAtomic(PacketPtr pkt) { return 0; }
|
|
|
|
virtual void
|
|
recvFunctional(PacketPtr pkt)
|
|
{
|
|
}
|
|
|
|
virtual void
|
|
recvRangeChange()
|
|
{
|
|
}
|
|
|
|
virtual void
|
|
recvReqRetry();
|
|
};
|
|
|
|
/** The port to access the Local Data Store
|
|
* Can be connected to a LDS object
|
|
*/
|
|
LDSPort *ldsPort = nullptr;
|
|
|
|
LDSPort *
|
|
getLdsPort() const
|
|
{
|
|
return ldsPort;
|
|
}
|
|
|
|
/** The memory port for SIMD data accesses.
|
|
* Can be connected to PhysMem for Ruby for timing simulations
|
|
*/
|
|
std::vector<DataPort*> memPort;
|
|
// port to the TLB hierarchy (i.e., the L1 TLB)
|
|
std::vector<DTLBPort*> tlbPort;
|
|
// port to the SQC (i.e. the I-cache)
|
|
SQCPort *sqcPort;
|
|
// port to the SQC TLB (there's a separate TLB for each I-cache)
|
|
ITLBPort *sqcTLBPort;
|
|
|
|
virtual BaseMasterPort&
|
|
getMasterPort(const std::string &if_name, PortID idx)
|
|
{
|
|
if (if_name == "memory_port") {
|
|
memPort[idx] = new DataPort(csprintf("%s-port%d", name(), idx),
|
|
this, idx);
|
|
return *memPort[idx];
|
|
} else if (if_name == "translation_port") {
|
|
tlbPort[idx] = new DTLBPort(csprintf("%s-port%d", name(), idx),
|
|
this, idx);
|
|
return *tlbPort[idx];
|
|
} else if (if_name == "sqc_port") {
|
|
sqcPort = new SQCPort(csprintf("%s-port%d", name(), idx),
|
|
this, idx);
|
|
return *sqcPort;
|
|
} else if (if_name == "sqc_tlb_port") {
|
|
sqcTLBPort = new ITLBPort(csprintf("%s-port", name()), this);
|
|
return *sqcTLBPort;
|
|
} else if (if_name == "ldsPort") {
|
|
if (ldsPort) {
|
|
fatal("an LDS port was already allocated");
|
|
}
|
|
ldsPort = new LDSPort(csprintf("%s-port", name()), this, idx);
|
|
return *ldsPort;
|
|
} else {
|
|
panic("incorrect port name");
|
|
}
|
|
}
|
|
|
|
// xact_cas_load()
|
|
class waveIdentifier
|
|
{
|
|
public:
|
|
waveIdentifier() { }
|
|
waveIdentifier(int _simdId, int _wfSlotId)
|
|
: simdId(_simdId), wfSlotId(_wfSlotId) { }
|
|
|
|
int simdId;
|
|
int wfSlotId;
|
|
};
|
|
|
|
class waveQueue
|
|
{
|
|
public:
|
|
std::list<waveIdentifier> waveIDQueue;
|
|
};
|
|
std::map<unsigned, waveQueue> xactCasLoadMap;
|
|
|
|
uint64_t getAndIncSeqNum() { return globalSeqNum++; }
|
|
|
|
private:
|
|
uint64_t globalSeqNum;
|
|
int wavefrontSize;
|
|
};
|
|
|
|
#endif // __COMPUTE_UNIT_HH__
|