The TLB-related code is generally architecture dependent and should live in the arch directory to signify that. --HG-- rename : src/sim/BaseTLB.py => src/arch/generic/BaseTLB.py rename : src/sim/tlb.cc => src/arch/generic/tlb.cc rename : src/sim/tlb.hh => src/arch/generic/tlb.hh
108 lines
4 KiB
C++
Executable file
108 lines
4 KiB
C++
Executable file
/*
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* Copyright (c) 2010-2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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* Giacomo Gabrielli
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*/
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#ifndef __ARCH_ARM_STAGE2_LOOKUP_HH__
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#define __ARCH_ARM_STAGE2_LOOKUP_HH__
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#include <list>
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#include "arch/arm/system.hh"
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#include "arch/arm/table_walker.hh"
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#include "arch/arm/tlb.hh"
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#include "mem/request.hh"
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class ThreadContext;
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namespace ArmISA {
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class Translation;
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class TLB;
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class Stage2LookUp : public BaseTLB::Translation
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{
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private:
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TLB *stage1Tlb;
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TLB *stage2Tlb;
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TlbEntry stage1Te;
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RequestPtr s1Req;
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TLB::Translation *transState;
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BaseTLB::Mode mode;
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bool timing;
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bool functional;
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TLB::ArmTranslationType tranType;
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TlbEntry *stage2Te;
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Request req;
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Fault fault;
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bool complete;
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bool selfDelete;
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public:
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Stage2LookUp(TLB *s1Tlb, TLB *s2Tlb, TlbEntry s1Te, RequestPtr _req,
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TLB::Translation *_transState, BaseTLB::Mode _mode, bool _timing,
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bool _functional, TLB::ArmTranslationType _tranType) :
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stage1Tlb(s1Tlb), stage2Tlb(s2Tlb), stage1Te(s1Te), s1Req(_req),
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transState(_transState), mode(_mode), timing(_timing),
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functional(_functional), tranType(_tranType), stage2Te(nullptr),
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fault(NoFault), complete(false), selfDelete(false)
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{
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req.setVirt(0, s1Te.pAddr(s1Req->getVaddr()), s1Req->getSize(),
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s1Req->getFlags(), s1Req->masterId(), 0);
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}
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Fault getTe(ThreadContext *tc, TlbEntry *destTe);
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void mergeTe(RequestPtr req, BaseTLB::Mode mode);
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void setSelfDelete() { selfDelete = true; }
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bool isComplete() const { return complete; }
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void markDelayed() {}
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void finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
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BaseTLB::Mode mode);
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};
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} // namespace ArmISA
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#endif //__ARCH_ARM_STAGE2_LOOKUP_HH__
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