567a9b0a08
This also allows checkpointing of a Kvm GIC via the Pl390 model. Change-Id: Ic85d81cfefad630617491b732398f5e6a5f34c0b Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2444 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
455 lines
12 KiB
C++
455 lines
12 KiB
C++
/*
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* Copyright (c) 2015-2017 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andreas Sandberg
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* Curtis Dunham
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*/
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#include "arch/arm/kvm/gic.hh"
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#include <linux/kvm.h>
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#include "arch/arm/kvm/base_cpu.hh"
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#include "debug/GIC.hh"
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#include "debug/Interrupt.hh"
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#include "params/MuxingKvmGic.hh"
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KvmKernelGicV2::KvmKernelGicV2(KvmVM &_vm, Addr cpu_addr, Addr dist_addr,
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unsigned it_lines)
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: cpuRange(RangeSize(cpu_addr, KVM_VGIC_V2_CPU_SIZE)),
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distRange(RangeSize(dist_addr, KVM_VGIC_V2_DIST_SIZE)),
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vm(_vm),
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kdev(vm.createDevice(KVM_DEV_TYPE_ARM_VGIC_V2))
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{
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kdev.setAttr<uint64_t>(
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KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_DIST, dist_addr);
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kdev.setAttr<uint64_t>(
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KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V2_ADDR_TYPE_CPU, cpu_addr);
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kdev.setAttr<uint32_t>(KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0, it_lines);
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}
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KvmKernelGicV2::~KvmKernelGicV2()
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{
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}
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void
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KvmKernelGicV2::setSPI(unsigned spi)
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{
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setIntState(KVM_ARM_IRQ_TYPE_SPI, 0, spi, true);
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}
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void
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KvmKernelGicV2::clearSPI(unsigned spi)
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{
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setIntState(KVM_ARM_IRQ_TYPE_SPI, 0, spi, false);
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}
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void
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KvmKernelGicV2::setPPI(unsigned vcpu, unsigned ppi)
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{
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setIntState(KVM_ARM_IRQ_TYPE_PPI, vcpu, ppi, true);
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}
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void
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KvmKernelGicV2::clearPPI(unsigned vcpu, unsigned ppi)
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{
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setIntState(KVM_ARM_IRQ_TYPE_PPI, vcpu, ppi, false);
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}
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void
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KvmKernelGicV2::setIntState(unsigned type, unsigned vcpu, unsigned irq,
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bool high)
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{
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assert(type <= KVM_ARM_IRQ_TYPE_MASK);
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assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK);
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assert(irq <= KVM_ARM_IRQ_NUM_MASK);
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const uint32_t line(
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(type << KVM_ARM_IRQ_TYPE_SHIFT) |
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(vcpu << KVM_ARM_IRQ_VCPU_SHIFT) |
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(irq << KVM_ARM_IRQ_NUM_SHIFT));
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vm.setIRQLine(line, high);
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}
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uint32_t
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KvmKernelGicV2::getGicReg(unsigned group, unsigned vcpu, unsigned offset)
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{
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uint64_t reg;
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assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK);
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const uint32_t attr(
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(vcpu << KVM_DEV_ARM_VGIC_CPUID_SHIFT) |
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(offset << KVM_DEV_ARM_VGIC_OFFSET_SHIFT));
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kdev.getAttrPtr(group, attr, ®);
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return (uint32_t) reg;
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}
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void
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KvmKernelGicV2::setGicReg(unsigned group, unsigned vcpu, unsigned offset,
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unsigned value)
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{
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uint64_t reg = value;
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assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK);
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const uint32_t attr(
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(vcpu << KVM_DEV_ARM_VGIC_CPUID_SHIFT) |
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(offset << KVM_DEV_ARM_VGIC_OFFSET_SHIFT));
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kdev.setAttrPtr(group, attr, ®);
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}
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uint32_t
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KvmKernelGicV2::readDistributor(ContextID ctx, Addr daddr)
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{
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auto vcpu = vm.contextIdToVCpuId(ctx);
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return getGicReg(KVM_DEV_ARM_VGIC_GRP_DIST_REGS, vcpu, daddr);
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}
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uint32_t
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KvmKernelGicV2::readCpu(ContextID ctx, Addr daddr)
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{
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auto vcpu = vm.contextIdToVCpuId(ctx);
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return getGicReg(KVM_DEV_ARM_VGIC_GRP_CPU_REGS, vcpu, daddr);
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}
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void
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KvmKernelGicV2::writeDistributor(ContextID ctx, Addr daddr, uint32_t data)
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{
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auto vcpu = vm.contextIdToVCpuId(ctx);
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setGicReg(KVM_DEV_ARM_VGIC_GRP_DIST_REGS, vcpu, daddr, data);
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}
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void
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KvmKernelGicV2::writeCpu(ContextID ctx, Addr daddr, uint32_t data)
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{
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auto vcpu = vm.contextIdToVCpuId(ctx);
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setGicReg(KVM_DEV_ARM_VGIC_GRP_CPU_REGS, vcpu, daddr, data);
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}
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MuxingKvmGic::MuxingKvmGic(const MuxingKvmGicParams *p)
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: Pl390(p),
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system(*p->system),
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kernelGic(nullptr),
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usingKvm(false)
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{
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if (auto vm = system.getKvmVM()) {
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kernelGic = new KvmKernelGicV2(*vm, p->cpu_addr, p->dist_addr,
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p->it_lines);
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}
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}
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MuxingKvmGic::~MuxingKvmGic()
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{
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}
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void
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MuxingKvmGic::loadState(CheckpointIn &cp)
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{
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Pl390::loadState(cp);
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}
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void
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MuxingKvmGic::startup()
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{
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Pl390::startup();
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usingKvm = (kernelGic != nullptr) && validKvmEnvironment();
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if (usingKvm)
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fromPl390ToKvm();
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}
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DrainState
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MuxingKvmGic::drain()
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{
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if (usingKvm)
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fromKvmToPl390();
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return Pl390::drain();
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}
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void
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MuxingKvmGic::drainResume()
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{
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Pl390::drainResume();
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bool use_kvm = (kernelGic != nullptr) && validKvmEnvironment();
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if (use_kvm != usingKvm) {
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// Should only occur due to CPU switches
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if (use_kvm) // from simulation to KVM emulation
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fromPl390ToKvm();
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// otherwise, drain() already sync'd the state back to the Pl390
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usingKvm = use_kvm;
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}
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}
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void
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MuxingKvmGic::serialize(CheckpointOut &cp) const
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{
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// drain() already ensured Pl390 updated with KvmGic state if necessary
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Pl390::serialize(cp);
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}
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void
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MuxingKvmGic::unserialize(CheckpointIn &cp)
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{
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Pl390::unserialize(cp);
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}
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Tick
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MuxingKvmGic::read(PacketPtr pkt)
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{
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if (!usingKvm)
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return Pl390::read(pkt);
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panic("MuxingKvmGic: PIO from gem5 is currently unsupported\n");
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}
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Tick
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MuxingKvmGic::write(PacketPtr pkt)
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{
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if (!usingKvm)
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return Pl390::write(pkt);
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panic("MuxingKvmGic: PIO from gem5 is currently unsupported\n");
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}
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void
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MuxingKvmGic::sendInt(uint32_t num)
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{
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if (!usingKvm)
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return Pl390::sendInt(num);
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DPRINTF(Interrupt, "Set SPI %d\n", num);
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kernelGic->setSPI(num);
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}
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void
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MuxingKvmGic::clearInt(uint32_t num)
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{
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if (!usingKvm)
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return Pl390::clearInt(num);
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DPRINTF(Interrupt, "Clear SPI %d\n", num);
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kernelGic->clearSPI(num);
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}
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void
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MuxingKvmGic::sendPPInt(uint32_t num, uint32_t cpu)
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{
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if (!usingKvm)
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return Pl390::sendPPInt(num, cpu);
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DPRINTF(Interrupt, "Set PPI %d:%d\n", cpu, num);
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kernelGic->setPPI(cpu, num);
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}
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void
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MuxingKvmGic::clearPPInt(uint32_t num, uint32_t cpu)
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{
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if (!usingKvm)
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return Pl390::clearPPInt(num, cpu);
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DPRINTF(Interrupt, "Clear PPI %d:%d\n", cpu, num);
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kernelGic->clearPPI(cpu, num);
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}
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bool
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MuxingKvmGic::validKvmEnvironment() const
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{
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if (system.threadContexts.empty())
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return false;
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for (auto tc : system.threadContexts) {
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if (dynamic_cast<BaseArmKvmCPU*>(tc->getCpuPtr()) == nullptr) {
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return false;
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}
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}
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return true;
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}
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void
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MuxingKvmGic::copyDistRegister(BaseGicRegisters* from, BaseGicRegisters* to,
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ContextID ctx, Addr daddr)
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{
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auto val = from->readDistributor(ctx, daddr);
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DPRINTF(GIC, "copy dist 0x%x 0x%08x\n", daddr, val);
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to->writeDistributor(ctx, daddr, val);
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}
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void
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MuxingKvmGic::copyCpuRegister(BaseGicRegisters* from, BaseGicRegisters* to,
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ContextID ctx, Addr daddr)
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{
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auto val = from->readCpu(ctx, daddr);
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DPRINTF(GIC, "copy cpu 0x%x 0x%08x\n", daddr, val);
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to->writeCpu(ctx, daddr, val);
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}
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void
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MuxingKvmGic::copyBankedDistRange(BaseGicRegisters* from, BaseGicRegisters* to,
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Addr daddr, size_t size)
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{
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for (int ctx = 0; ctx < system._numContexts; ++ctx)
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for (auto a = daddr; a < daddr + size; a += 4)
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copyDistRegister(from, to, ctx, a);
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}
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void
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MuxingKvmGic::clearBankedDistRange(BaseGicRegisters* to,
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Addr daddr, size_t size)
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{
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for (int ctx = 0; ctx < system._numContexts; ++ctx)
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for (auto a = daddr; a < daddr + size; a += 4)
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to->writeDistributor(ctx, a, 0xFFFFFFFF);
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}
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void
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MuxingKvmGic::copyDistRange(BaseGicRegisters* from, BaseGicRegisters* to,
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Addr daddr, size_t size)
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{
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for (auto a = daddr; a < daddr + size; a += 4)
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copyDistRegister(from, to, 0, a);
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}
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void
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MuxingKvmGic::clearDistRange(BaseGicRegisters* to,
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Addr daddr, size_t size)
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{
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for (auto a = daddr; a < daddr + size; a += 4)
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to->writeDistributor(0, a, 0xFFFFFFFF);
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}
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void
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MuxingKvmGic::copyGicState(BaseGicRegisters* from, BaseGicRegisters* to)
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{
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Addr set, clear;
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size_t size;
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/// CPU state (GICC_*)
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// Copy CPU Interface Control Register (CTLR),
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// Interrupt Priority Mask Register (PMR), and
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// Binary Point Register (BPR)
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for (int ctx = 0; ctx < system._numContexts; ++ctx) {
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copyCpuRegister(from, to, ctx, GICC_CTLR);
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copyCpuRegister(from, to, ctx, GICC_PMR);
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copyCpuRegister(from, to, ctx, GICC_BPR);
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}
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/// Distributor state (GICD_*)
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// Copy Distributor Control Register (CTLR)
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copyDistRegister(from, to, 0, GICD_CTLR);
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// Copy interrupt-enabled statuses (I[CS]ENABLERn; R0 is per-CPU banked)
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set = Pl390::GICD_ISENABLER.start();
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clear = Pl390::GICD_ICENABLER.start();
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size = Pl390::itLines / 8;
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clearBankedDistRange(to, clear, 4);
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copyBankedDistRange(from, to, set, 4);
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set += 4, clear += 4, size -= 4;
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clearDistRange(to, clear, size);
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copyDistRange(from, to, set, size);
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// Copy pending interrupts (I[CS]PENDRn; R0 is per-CPU banked)
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set = Pl390::GICD_ISPENDR.start();
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clear = Pl390::GICD_ICPENDR.start();
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size = Pl390::itLines / 8;
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clearBankedDistRange(to, clear, 4);
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copyBankedDistRange(from, to, set, 4);
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set += 4, clear += 4, size -= 4;
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clearDistRange(to, clear, size);
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copyDistRange(from, to, set, size);
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// Copy active interrupts (I[CS]ACTIVERn; R0 is per-CPU banked)
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set = Pl390::GICD_ISACTIVER.start();
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clear = Pl390::GICD_ICACTIVER.start();
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size = Pl390::itLines / 8;
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clearBankedDistRange(to, clear, 4);
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copyBankedDistRange(from, to, set, 4);
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set += 4, clear += 4, size -= 4;
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clearDistRange(to, clear, size);
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copyDistRange(from, to, set, size);
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// Copy interrupt priorities (IPRIORITYRn; R0-7 are per-CPU banked)
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set = Pl390::GICD_IPRIORITYR.start();
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copyBankedDistRange(from, to, set, 32);
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set += 32;
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size = Pl390::itLines - 32;
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copyDistRange(from, to, set, size);
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// Copy interrupt processor target regs (ITARGETRn; R0-7 are read-only)
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set = Pl390::GICD_ITARGETSR.start() + 32;
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size = Pl390::itLines - 32;
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copyDistRange(from, to, set, size);
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// Copy interrupt configuration registers (ICFGRn)
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set = Pl390::GICD_ICFGR.start();
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size = Pl390::itLines / 4;
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copyDistRange(from, to, set, size);
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}
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void
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MuxingKvmGic::fromPl390ToKvm()
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{
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copyGicState(static_cast<Pl390*>(this), kernelGic);
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}
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void
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MuxingKvmGic::fromKvmToPl390()
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{
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copyGicState(kernelGic, static_cast<Pl390*>(this));
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// the values read for the Interrupt Priority Mask Register (PMR)
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// have been shifted by three bits due to its having been emulated by
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// a VGIC with only 5 PMR bits in its VMCR register. Presently the
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// Linux kernel does not repair this inaccuracy, so we correct it here.
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for (int cpu = 0; cpu < system._numContexts; ++cpu) {
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cpuPriority[cpu] <<= 3;
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assert((cpuPriority[cpu] & ~0xff) == 0);
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}
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}
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MuxingKvmGic *
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MuxingKvmGicParams::create()
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{
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return new MuxingKvmGic(this);
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}
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