ca0fd665dc
Names of DRAM configurations were updated to reflect both
the channel and device data width.
Previous naming format was:
<DEVICE_TYPE>_<DATA_RATE>_<CHANNEL_WIDTH>
The following nomenclature is now used:
<DEVICE_TYPE>_<DATA_RATE>_<n>x<w>
where n = The number of devices per rank on the channel
x = Device width
Total channel width can be calculated by n*w
Example:
A 64-bit DDR4, 2400 channel consisting of 4-bit devices:
n = 16
w = 4
The resulting configuration name is:
DDR4_2400_16x4
Updated scripts to match new naming convention.
Added unique configurations for DDR4 for:
1) 16x4
2) 8x8
3) 4x16
Change-Id: Ibd7f763b7248835c624309143cb9fc29d56a69d1
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
230 lines
8.8 KiB
Python
230 lines
8.8 KiB
Python
# Copyright (c) 2013 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Andreas Sandberg
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# Andreas Hansson
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import m5.objects
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import inspect
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import sys
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import HMC
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from textwrap import TextWrapper
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# Dictionary of mapping names of real memory controller models to
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# classes.
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_mem_classes = {}
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def is_mem_class(cls):
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"""Determine if a class is a memory controller that can be instantiated"""
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# We can't use the normal inspect.isclass because the ParamFactory
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# and ProxyFactory classes have a tendency to confuse it.
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try:
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return issubclass(cls, m5.objects.AbstractMemory) and \
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not cls.abstract
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except TypeError:
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return False
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def get(name):
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"""Get a memory class from a user provided class name."""
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try:
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mem_class = _mem_classes[name]
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return mem_class
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except KeyError:
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print "%s is not a valid memory controller." % (name,)
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sys.exit(1)
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def print_mem_list():
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"""Print a list of available memory classes."""
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print "Available memory classes:"
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doc_wrapper = TextWrapper(initial_indent="\t\t", subsequent_indent="\t\t")
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for name, cls in _mem_classes.items():
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print "\t%s" % name
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# Try to extract the class documentation from the class help
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# string.
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doc = inspect.getdoc(cls)
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if doc:
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for line in doc_wrapper.wrap(doc):
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print line
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def mem_names():
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"""Return a list of valid memory names."""
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return _mem_classes.keys()
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# Add all memory controllers in the object hierarchy.
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for name, cls in inspect.getmembers(m5.objects, is_mem_class):
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_mem_classes[name] = cls
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def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size):
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"""
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Helper function for creating a single memoy controller from the given
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options. This function is invoked multiple times in config_mem function
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to create an array of controllers.
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"""
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import math
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intlv_low_bit = int(math.log(intlv_size, 2))
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# Use basic hashing for the channel selection, and preferably use
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# the lower tag bits from the last level cache. As we do not know
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# the details of the caches here, make an educated guess. 4 MByte
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# 4-way associative with 64 byte cache lines is 6 offset bits and
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# 14 index bits.
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xor_low_bit = 20
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# Create an instance so we can figure out the address
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# mapping and row-buffer size
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ctrl = cls()
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# Only do this for DRAMs
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if issubclass(cls, m5.objects.DRAMCtrl):
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# Inform each controller how many channels to account
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# for
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ctrl.channels = nbr_mem_ctrls
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# If the channel bits are appearing after the column
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# bits, we need to add the appropriate number of bits
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# for the row buffer size
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if ctrl.addr_mapping.value == 'RoRaBaChCo':
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# This computation only really needs to happen
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# once, but as we rely on having an instance we
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# end up having to repeat it for each and every
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# one
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rowbuffer_size = ctrl.device_rowbuffer_size.value * \
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ctrl.devices_per_rank.value
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intlv_low_bit = int(math.log(rowbuffer_size, 2))
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# We got all we need to configure the appropriate address
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# range
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ctrl.range = m5.objects.AddrRange(r.start, size = r.size(),
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intlvHighBit = \
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intlv_low_bit + intlv_bits - 1,
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xorHighBit = \
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xor_low_bit + intlv_bits - 1,
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intlvBits = intlv_bits,
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intlvMatch = i)
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return ctrl
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def config_mem(options, system):
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"""
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Create the memory controllers based on the options and attach them.
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If requested, we make a multi-channel configuration of the
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selected memory controller class by creating multiple instances of
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the specific class. The individual controllers have their
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parameters set such that the address range is interleaved between
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them.
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"""
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if ( options.mem_type == "HMC_2500_1x32"):
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HMChost = HMC.config_host_hmc(options, system)
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HMC.config_hmc(options, system, HMChost.hmc_host)
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subsystem = system.hmc_dev
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xbar = system.hmc_dev.xbar
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else:
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subsystem = system
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xbar = system.membus
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if options.tlm_memory:
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system.external_memory = m5.objects.ExternalSlave(
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port_type="tlm_slave",
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port_data=options.tlm_memory,
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port=system.membus.master,
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addr_ranges=system.mem_ranges)
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system.kernel_addr_check = False
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return
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if options.external_memory_system:
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subsystem.external_memory = m5.objects.ExternalSlave(
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port_type=options.external_memory_system,
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port_data="init_mem0", port=xbar.master,
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addr_ranges=system.mem_ranges)
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subsystem.kernel_addr_check = False
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return
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nbr_mem_ctrls = options.mem_channels
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import math
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from m5.util import fatal
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intlv_bits = int(math.log(nbr_mem_ctrls, 2))
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if 2 ** intlv_bits != nbr_mem_ctrls:
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fatal("Number of memory channels must be a power of 2")
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cls = get(options.mem_type)
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mem_ctrls = []
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if options.elastic_trace_en and not issubclass(cls, \
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m5.objects.SimpleMemory):
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fatal("When elastic trace is enabled, configure mem-type as "
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"simple-mem.")
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# The default behaviour is to interleave memory channels on 128
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# byte granularity, or cache line granularity if larger than 128
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# byte. This value is based on the locality seen across a large
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# range of workloads.
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intlv_size = max(128, system.cache_line_size.value)
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# For every range (most systems will only have one), create an
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# array of controllers and set their parameters to match their
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# address mapping in the case of a DRAM
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for r in system.mem_ranges:
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for i in xrange(nbr_mem_ctrls):
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mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits,
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intlv_size)
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# Set the number of ranks based on the command-line
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# options if it was explicitly set
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if issubclass(cls, m5.objects.DRAMCtrl) and \
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options.mem_ranks:
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mem_ctrl.ranks_per_channel = options.mem_ranks
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if options.elastic_trace_en:
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mem_ctrl.latency = '1ns'
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print "For elastic trace, over-riding Simple Memory " \
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"latency to 1ns."
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mem_ctrls.append(mem_ctrl)
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subsystem.mem_ctrls = mem_ctrls
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# Connect the controllers to the membus
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for i in xrange(len(subsystem.mem_ctrls)):
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if (options.mem_type == "HMC_2500_1x32"):
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subsystem.mem_ctrls[i].port = xbar[i/4].master
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else:
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subsystem.mem_ctrls[i].port = xbar.master
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