Mitch Hayenga c7dbd5e768 mem: Make LL/SC locks fine grained ... The current implementation in gem5 just keeps a list of locks per cacheline. Due to this, a store to a non-overlapping portion of the cacheline can cause an LL/SC pair to fail. This patch simply adds an address range to the lock structure, so that the lock is only invalidated if the store overlaps the lock range.		2013-01-08 08:54:07 -05:00
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arch	cpu: Flush TLBs on switchOut()	2013-01-07 13:05:48 -05:00
base	scons: Enforce gcc >= 4.4 or clang >= 2.9 and c++0x support	2013-01-07 13:05:39 -05:00
cpu	cpu: Unify the serialization code for all of the CPU models	2013-01-07 13:05:52 -05:00
dev	dev: Fix infinite recursion in DMA devices	2013-01-07 16:56:39 -05:00
doc	MEM: Put memory system document into doxygen	2012-09-25 11:49:41 -05:00
doxygen	MEM: Put memory system document into doxygen	2012-09-25 11:49:41 -05:00
kern	base: Encapsulate the underlying fields in AddrRange	2013-01-07 13:05:38 -05:00
mem	mem: Make LL/SC locks fine grained	2013-01-08 08:54:07 -05:00
proto	base: Add wrapped protobuf input stream	2013-01-07 13:05:37 -05:00
python	stats: Fix swig wrapping for Tick in stats	2013-01-07 16:56:36 -05:00
sim	stats: Fix swig wrapping for Tick in stats	2013-01-07 16:56:36 -05:00
unittest	AddrRange: Transition from Range<T> to AddrRange	2012-09-19 06:15:44 -04:00
Doxyfile	Doxygen: Update the version of the Doxyfile	2012-10-11 06:38:42 -04:00
SConscript	scons: Remove stale compiler options	2013-01-07 13:05:39 -05:00