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gem5/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
Andreas Hansson c4e91289ae stats: Bump stats for filter, crossbar and config changes 
This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
2014-09-20 17:18:53 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 0.000019 # Number of seconds simulated
sim_ticks 18857500 # Number of ticks simulated
final_tick 18857500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 98075 # Simulator instruction rate (inst/s)
host_op_rate 98051 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 319158839 # Simulator tick rate (ticks/s)
host_mem_usage 285824 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
sim_insts 5792 # Number of instructions simulated
sim_ops 5792 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 21952 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory
system.physmem.bytes_read::total 28416 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 21952 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 21952 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory
system.physmem.num_reads::total 444 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1164099165 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 342781387 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1506880552 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1164099165 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1164099165 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1164099165 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 342781387 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1506880552 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 444 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 28416 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 28416 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 71 # Per bank write bursts
system.physmem.perBankRdBursts::1 42 # Per bank write bursts
system.physmem.perBankRdBursts::2 55 # Per bank write bursts
system.physmem.perBankRdBursts::3 58 # Per bank write bursts
system.physmem.perBankRdBursts::4 53 # Per bank write bursts
system.physmem.perBankRdBursts::5 61 # Per bank write bursts
system.physmem.perBankRdBursts::6 52 # Per bank write bursts
system.physmem.perBankRdBursts::7 10 # Per bank write bursts
system.physmem.perBankRdBursts::8 9 # Per bank write bursts
system.physmem.perBankRdBursts::9 28 # Per bank write bursts
system.physmem.perBankRdBursts::10 1 # Per bank write bursts
system.physmem.perBankRdBursts::11 0 # Per bank write bursts
system.physmem.perBankRdBursts::12 0 # Per bank write bursts
system.physmem.perBankRdBursts::13 0 # Per bank write bursts
system.physmem.perBankRdBursts::14 4 # Per bank write bursts
system.physmem.perBankRdBursts::15 0 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 18724000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 444 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 240 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 333.772152 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 192.283764 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 349.893315 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 30 37.97% 37.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 17 21.52% 59.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 8 10.13% 69.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 4 5.06% 74.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 3 3.80% 78.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 2 2.53% 81.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1 1.27% 82.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 3 3.80% 86.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 11 13.92% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation
system.physmem.totQLat 3635500 # Total ticks spent queuing
system.physmem.totMemAccLat 11960500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers
system.physmem.avgQLat 8188.06 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 26938.06 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1506.88 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1506.88 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 11.77 # Data bus utilization in percentage
system.physmem.busUtilRead 11.77 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 356 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.18 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 42171.17 # Average gap between requests
system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 11000 # Time in different power states
system.physmem.memoryStateTime::REF 520000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 15315250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.membus.trans_dist::ReadReq 397 # Transaction distribution
system.membus.trans_dist::ReadResp 397 # Transaction distribution
system.membus.trans_dist::ReadExReq 47 # Transaction distribution
system.membus.trans_dist::ReadExResp 47 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 888 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 888 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 444 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 444 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 444 # Request fanout histogram
system.membus.reqLayer0.occupancy 555500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
system.membus.respLayer1.occupancy 4160750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 22.1 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.branchPred.lookups 2332 # Number of BP lookups
system.cpu.branchPred.condPredicted 1883 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 415 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 1931 # Number of BTB lookups
system.cpu.branchPred.BTBHits 661 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 34.230968 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 219 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 31 # Number of incorrect RAS predictions.
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 9 # Number of system calls
system.cpu.numCycles 37716 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 7977 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 13500 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2332 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 880 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 3710 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 864 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 159 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 1829 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 300 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 12303 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.097293 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.503786 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 9940 80.79% 80.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 189 1.54% 82.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 216 1.76% 84.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 152 1.24% 85.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 247 2.01% 87.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 139 1.13% 88.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 253 2.06% 90.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 114 0.93% 91.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1053 8.56% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 12303 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.061831 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.357938 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 7389 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 2550 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 1951 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 283 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 336 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 150 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 11555 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 471 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 283 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 7548 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 922 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 607 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 1916 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 1027 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 11189 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 968 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 9624 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 18111 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 18085 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 4626 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 27 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 351 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2013 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1831 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 10314 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 63 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 9108 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 73 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 4178 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3333 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 12303 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.740307 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.567670 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 9185 74.66% 74.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 929 7.55% 82.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 638 5.19% 87.39% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 470 3.82% 91.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 430 3.50% 94.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 294 2.39% 97.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 241 1.96% 99.06% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 71 0.58% 99.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 45 0.37% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 12303 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 10 3.98% 3.98% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 3.98% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.98% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.98% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.98% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.98% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.98% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.98% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.98% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 122 48.61% 52.59% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 119 47.41% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 5539 60.81% 60.81% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 60.81% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 60.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.84% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 1909 20.96% 81.80% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1658 18.20% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 9108 # Type of FU issued
system.cpu.iq.rate 0.241489 # Inst issue rate
system.cpu.iq.fu_busy_cnt 251 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.027558 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 30781 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 14531 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 8273 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 31 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 9325 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 79 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1052 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 785 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 283 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 835 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 80 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 10377 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 18 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2013 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1831 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 11 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 70 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 277 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 346 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 8702 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 1775 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 406 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 3329 # number of memory reference insts executed
system.cpu.iew.exec_branches 1361 # Number of branches executed
system.cpu.iew.exec_stores 1554 # Number of stores executed
system.cpu.iew.exec_rate 0.230724 # Inst execution rate
system.cpu.iew.wb_sent 8430 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 8300 # cumulative count of insts written-back
system.cpu.iew.wb_producers 4483 # num instructions producing a value
system.cpu.iew.wb_consumers 7102 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.220066 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.631231 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 4587 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 277 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 11593 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.499612 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.370164 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 9440 81.43% 81.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 839 7.24% 88.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 524 4.52% 93.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 224 1.93% 95.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 167 1.44% 96.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 112 0.97% 97.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 115 0.99% 98.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 61 0.53% 99.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 111 0.96% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 11593 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5792 # Number of instructions committed
system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 2007 # Number of memory references committed
system.cpu.commit.loads 961 # Number of loads committed
system.cpu.commit.membars 7 # Number of memory barriers committed
system.cpu.commit.branches 1037 # Number of branches committed
system.cpu.commit.fp_insts 22 # Number of committed floating point instructions.
system.cpu.commit.int_insts 5698 # Number of committed integer instructions.
system.cpu.commit.function_calls 103 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 3783 65.31% 65.31% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 0 0.00% 65.31% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 2 0.03% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 961 16.59% 81.94% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 5792 # Class of committed instruction
system.cpu.commit.bw_lim_events 111 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 21861 # The number of ROB reads
system.cpu.rob.rob_writes 21469 # The number of ROB writes
system.cpu.timesIdled 245 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 25413 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5792 # Number of Instructions Simulated
system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 6.511740 # CPI: Cycles Per Instruction
system.cpu.cpi_total 6.511740 # CPI: Total CPI of All Threads
system.cpu.ipc 0.153569 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.153569 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 13743 # number of integer regfile reads
system.cpu.int_regfile_writes 7176 # number of integer regfile writes
system.cpu.fp_regfile_reads 25 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.toL2Bus.trans_dist::ReadReq 405 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 903 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 28864 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 452 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 452 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 584250 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 162500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 170.472010 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1391 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 3.985673 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 170.472010 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.083238 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.083238 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 4007 # Number of tag accesses
system.cpu.icache.tags.data_accesses 4007 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 1391 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1391 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1391 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1391 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1391 # number of overall hits
system.cpu.icache.overall_hits::total 1391 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 438 # number of ReadReq misses
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system.cpu.icache.demand_miss_latency::total 29787250 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 29787250 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 29787250 # number of overall miss cycles
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system.cpu.icache.demand_avg_miss_latency::total 68007.420091 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 68007.420091 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 68007.420091 # average overall miss latency
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system.cpu.icache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses
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system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_miss_latency::total 24058750 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68739.285714 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::total 68739.285714 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68739.285714 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 68739.285714 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_miss_latency::total 67366.694690 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 597 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.500000 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 292 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 292 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4203250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4203250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3795248 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3795248 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7998498 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7998498 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7998498 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7998498 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032993 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032993 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.037597 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.037597 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76422.727273 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76422.727273 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80749.957447 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80749.957447 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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