c4e91289ae
This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
1126 lines
127 KiB
Text
1126 lines
127 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000016 # Number of seconds simulated
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sim_ticks 16223000 # Number of ticks simulated
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final_tick 16223000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 55920 # Simulator instruction rate (inst/s)
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host_op_rate 65484 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 197542740 # Simulator tick rate (ticks/s)
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host_mem_usage 304472 # Number of bytes of host memory used
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host_seconds 0.08 # Real time elapsed on the host
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sim_insts 4591 # Number of instructions simulated
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sim_ops 5377 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory
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system.physmem.bytes_read::total 25408 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 397 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1084879492 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 481291993 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1566171485 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1084879492 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1084879492 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1084879492 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 481291993 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 1566171485 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 397 # Number of read requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 25408 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 25408 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 90 # Per bank write bursts
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system.physmem.perBankRdBursts::1 46 # Per bank write bursts
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system.physmem.perBankRdBursts::2 20 # Per bank write bursts
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system.physmem.perBankRdBursts::3 43 # Per bank write bursts
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system.physmem.perBankRdBursts::4 18 # Per bank write bursts
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system.physmem.perBankRdBursts::5 32 # Per bank write bursts
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system.physmem.perBankRdBursts::6 35 # Per bank write bursts
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system.physmem.perBankRdBursts::7 10 # Per bank write bursts
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system.physmem.perBankRdBursts::8 4 # Per bank write bursts
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system.physmem.perBankRdBursts::9 8 # Per bank write bursts
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system.physmem.perBankRdBursts::10 28 # Per bank write bursts
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system.physmem.perBankRdBursts::11 42 # Per bank write bursts
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system.physmem.perBankRdBursts::12 9 # Per bank write bursts
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system.physmem.perBankRdBursts::13 6 # Per bank write bursts
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system.physmem.perBankRdBursts::14 0 # Per bank write bursts
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system.physmem.perBankRdBursts::15 6 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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system.physmem.perBankWrBursts::3 0 # Per bank write bursts
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system.physmem.perBankWrBursts::4 0 # Per bank write bursts
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system.physmem.perBankWrBursts::5 0 # Per bank write bursts
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system.physmem.perBankWrBursts::6 0 # Per bank write bursts
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system.physmem.perBankWrBursts::7 0 # Per bank write bursts
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system.physmem.perBankWrBursts::8 0 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 0 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 0 # Per bank write bursts
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system.physmem.perBankWrBursts::13 0 # Per bank write bursts
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system.physmem.perBankWrBursts::14 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 16156000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 397 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 209 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 396.190476 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 265.364013 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 334.900990 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 12 19.05% 19.05% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 16 25.40% 44.44% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 8 12.70% 57.14% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 9 14.29% 71.43% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation
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system.physmem.totQLat 3126000 # Total ticks spent queuing
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system.physmem.totMemAccLat 10569750 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 7874.06 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 26624.06 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 1566.17 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 1566.17 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 12.24 # Data bus utilization in percentage
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system.physmem.busUtilRead 12.24 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.84 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
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system.physmem.readRowHits 331 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 40695.21 # Average gap between requests
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system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined
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system.physmem.memoryStateTime::IDLE 11000 # Time in different power states
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system.physmem.memoryStateTime::REF 520000 # Time in different power states
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system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem.memoryStateTime::ACT 15315250 # Time in different power states
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system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.membus.trans_dist::ReadReq 355 # Transaction distribution
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system.membus.trans_dist::ReadResp 355 # Transaction distribution
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system.membus.trans_dist::ReadExReq 42 # Transaction distribution
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system.membus.trans_dist::ReadExResp 42 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes)
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system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes)
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system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes)
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system.membus.snoops 0 # Total snoops (count)
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system.membus.snoop_fanout::samples 397 # Request fanout histogram
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system.membus.snoop_fanout::mean 0 # Request fanout histogram
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system.membus.snoop_fanout::stdev 0 # Request fanout histogram
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system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
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system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::min_value 0 # Request fanout histogram
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system.membus.snoop_fanout::max_value 0 # Request fanout histogram
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system.membus.snoop_fanout::total 397 # Request fanout histogram
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system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 3.0 # Layer utilization (%)
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system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 22.8 # Layer utilization (%)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.branchPred.lookups 2638 # Number of BP lookups
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system.cpu.branchPred.condPredicted 1635 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 480 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 2101 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 783 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 37.267968 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 354 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions.
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system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.checker.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.checker.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.checker.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.checker.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.checker.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.checker.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.checker.dtb.hits 0 # DTB hits
|
|
system.cpu.checker.dtb.misses 0 # DTB misses
|
|
system.cpu.checker.dtb.accesses 0 # DTB accesses
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.checker.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.checker.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.checker.itb.read_hits 0 # DTB read hits
|
|
system.cpu.checker.itb.read_misses 0 # DTB read misses
|
|
system.cpu.checker.itb.write_hits 0 # DTB write hits
|
|
system.cpu.checker.itb.write_misses 0 # DTB write misses
|
|
system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.checker.itb.hits 0 # DTB hits
|
|
system.cpu.checker.itb.misses 0 # DTB misses
|
|
system.cpu.checker.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 13 # Number of system calls
|
|
system.cpu.checker.numCycles 5390 # number of cpu cycles simulated
|
|
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.numCycles 32447 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 7786 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 12484 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 2638 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 1137 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 4850 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 1010 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 2068 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 320 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 13433 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 1.098935 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 2.478489 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 10743 79.97% 79.97% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 265 1.97% 81.95% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 241 1.79% 83.74% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 235 1.75% 85.49% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 238 1.77% 87.26% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 291 2.17% 89.43% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 141 1.05% 90.48% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 175 1.30% 91.78% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 1104 8.22% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 13433 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.081302 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 0.384751 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 6529 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 4272 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 2145 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 138 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 349 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 390 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 12118 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 476 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 349 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 6736 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 846 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 2304 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 2064 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 1134 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 11483 # Number of instructions processed by rename
|
|
system.cpu.rename.IQFullEvents 163 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 117 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 963 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 11820 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 52846 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 12757 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 6326 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 43 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 443 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 2313 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 1639 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 10354 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 8358 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 4760 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 12835 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 13433 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.622199 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.376807 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 10179 75.78% 75.78% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 1183 8.81% 84.58% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 748 5.57% 90.15% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 453 3.37% 93.52% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 362 2.69% 96.22% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 286 2.13% 98.35% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 135 1.00% 99.35% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 64 0.48% 99.83% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 23 0.17% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 13433 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 9 5.33% 5.33% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 5.33% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 5.33% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.33% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.33% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.33% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 5.33% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.33% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.33% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.33% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.33% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.33% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.33% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.33% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.33% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 5.33% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.33% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 5.33% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.33% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.33% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.33% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.33% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.33% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.33% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.33% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.33% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.33% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.33% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.33% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 80 47.34% 52.66% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 80 47.34% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 5041 60.31% 60.31% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.39% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.39% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.39% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.39% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.39% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.39% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.39% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.39% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.39% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.39% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.39% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.39% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.39% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.39% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.39% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.39% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.39% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.39% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.39% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.39% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.39% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.39% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.39% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.39% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 60.42% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.42% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.42% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.42% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 2009 24.04% 84.46% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 1299 15.54% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 8358 # Type of FU issued
|
|
system.cpu.iq.rate 0.257589 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 169 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.020220 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 30275 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 15052 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 7570 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 99 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 128 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 31 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 8484 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 25 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1286 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 701 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 39 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 349 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 800 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 25 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 10411 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 2313 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 1639 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 112 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 252 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 364 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 8063 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 1908 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 295 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 11 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 3148 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 1457 # Number of branches executed
|
|
system.cpu.iew.exec_stores 1240 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.248498 # Inst execution rate
|
|
system.cpu.iew.wb_sent 7735 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 7601 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 3572 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 6998 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.234259 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.510432 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 5037 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 324 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 12552 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.428378 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.273949 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 10495 83.61% 83.61% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 893 7.11% 90.73% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 426 3.39% 94.12% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 211 1.68% 95.80% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 111 0.88% 96.69% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 212 1.69% 98.37% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 50 0.40% 98.77% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 37 0.29% 99.07% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 117 0.93% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 12552 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 4591 # Number of instructions committed
|
|
system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 1965 # Number of memory references committed
|
|
system.cpu.commit.loads 1027 # Number of loads committed
|
|
system.cpu.commit.membars 12 # Number of memory barriers committed
|
|
system.cpu.commit.branches 1007 # Number of branches committed
|
|
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 4624 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 82 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 3405 63.33% 63.33% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 4 0.07% 63.40% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.40% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.40% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.40% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.40% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.40% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.40% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.40% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.40% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.40% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.40% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.40% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.40% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.40% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.40% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.40% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.40% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.40% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.40% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.40% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.40% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.40% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.40% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.40% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 5377 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 22692 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 21719 # The number of ROB writes
|
|
system.cpu.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 19014 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 4591 # Number of Instructions Simulated
|
|
system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 7.067523 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 7.067523 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.141492 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.141492 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 7944 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 4420 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 31 # number of floating regfile reads
|
|
system.cpu.cc_regfile_reads 28734 # number of cc regfile reads
|
|
system.cpu.cc_regfile_writes 3302 # number of cc regfile writes
|
|
system.cpu.misc_regfile_reads 3189 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 9 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::9 441 100.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::10 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 9 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
|
|
system.cpu.icache.tags.replacements 1 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 150.722255 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 1666 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 5.666667 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 150.722255 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.073595 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.073595 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 293 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.143066 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 4430 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 4430 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 1666 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 1666 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 1666 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 1666 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 1666 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 1666 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 402 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 402 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 402 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 402 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 402 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 402 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25584000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 25584000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 25584000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 25584000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 25584000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 25584000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 2068 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 2068 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 2068 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 2068 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 2068 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 2068 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.194391 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.194391 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.194391 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.194391 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.194391 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.194391 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63641.791045 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 63641.791045 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 63641.791045 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 63641.791045 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 63641.791045 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 63641.791045 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 298 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 59.600000 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 294 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 294 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 294 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19740750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 19740750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19740750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 19740750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19740750 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 19740750 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.142166 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.142166 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.142166 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67145.408163 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67145.408163 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67145.408163 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 67145.408163 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67145.408163 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 67145.408163 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 188.125989 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 355 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 0.109859 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.336521 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 46.789468 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004313 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001428 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.005741 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010834 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 3925 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 3925 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 19 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 19 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 39 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 275 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 360 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 275 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 402 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 402 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19249250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6012750 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 25262000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3101750 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 3101750 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 19249250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 9114500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 28363750 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 19249250 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 9114500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 28363750 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 294 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 105 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 399 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 294 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 294 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.935374 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.809524 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.902256 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.935374 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.911565 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.935374 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.911565 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69997.272727 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70738.235294 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70172.222222 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73851.190476 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73851.190476 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69997.272727 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71767.716535 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 70556.592040 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69997.272727 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71767.716535 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 70556.592040 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 80 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 355 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 397 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15795750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4738000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20533750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2589250 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2589250 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15795750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7327250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 23123000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15795750 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7327250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 23123000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.761905 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889724 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57439.090909 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59225 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57841.549296 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61648.809524 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61648.809524 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57439.090909 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57439.090909 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 87.114563 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 2168 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 14.849315 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 87.114563 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.021268 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.021268 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 1551 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 1551 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 595 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 595 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 2146 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 2146 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 2146 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 2146 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 203 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 203 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 318 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 318 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 521 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 521 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 521 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 521 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11353493 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 11353493 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 20745500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 20745500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 32098993 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 32098993 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 32098993 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 32098993 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 1754 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 1754 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 2667 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 2667 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 2667 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 2667 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.115735 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.115735 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.348302 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.348302 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.195351 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.195351 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.195351 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.195351 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55928.536946 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 55928.536946 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65250 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65250 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 61610.351248 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 61610.351248 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 105 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.250000 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 98 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 276 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 276 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6247255 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6247255 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3144750 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3144750 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9392005 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 9392005 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9392005 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 9392005 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059863 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059863 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.055118 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.055118 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59497.666667 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59497.666667 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74875 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74875 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|