9bc132e473
The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
1344 lines
153 KiB
Text
1344 lines
153 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000262 # Number of seconds simulated
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sim_ticks 261623500 # Number of ticks simulated
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final_tick 261623500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 226128 # Simulator instruction rate (inst/s)
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host_op_rate 226126 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 89603226 # Simulator tick rate (ticks/s)
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host_mem_usage 289396 # Number of bytes of host memory used
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host_seconds 2.92 # Real time elapsed on the host
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sim_insts 660239 # Number of instructions simulated
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sim_ops 660239 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.inst 576 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.data 1024 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu3.inst 3392 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu3.data 1408 # Number of bytes read from this memory
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system.physmem.bytes_read::total 36608 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu2.inst 576 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu3.inst 3392 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.inst 9 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.data 16 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu3.inst 53 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu3.data 22 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 572 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu0.inst 69718508 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 40363347 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 1712384 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 3669395 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.inst 2201637 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.data 3914021 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu3.inst 12965196 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu3.data 5381780 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 139926268 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 69718508 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 1712384 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu2.inst 2201637 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu3.inst 12965196 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 86597725 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 69718508 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 40363347 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 1712384 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 3669395 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.inst 2201637 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.data 3914021 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu3.inst 12965196 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu3.data 5381780 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 139926268 # Total bandwidth to/from this memory (bytes/s)
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system.cpu0.workload.num_syscalls 89 # Number of system calls
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system.cpu0.numCycles 523247 # number of cpu cycles simulated
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu0.committedInsts 158010 # Number of instructions committed
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system.cpu0.committedOps 158010 # Number of ops (including micro ops) committed
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system.cpu0.num_int_alu_accesses 108832 # Number of integer alu accesses
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system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
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system.cpu0.num_func_calls 390 # number of times a function call or return occured
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system.cpu0.num_conditional_control_insts 25938 # number of instructions that are conditional controls
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system.cpu0.num_int_insts 108832 # number of integer instructions
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system.cpu0.num_fp_insts 0 # number of float instructions
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system.cpu0.num_int_register_reads 314654 # number of times the integer registers were read
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system.cpu0.num_int_register_writes 110438 # number of times the integer registers were written
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system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
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system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
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system.cpu0.num_mem_refs 73739 # number of memory refs
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system.cpu0.num_load_insts 48819 # Number of load instructions
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system.cpu0.num_store_insts 24920 # Number of store instructions
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system.cpu0.num_idle_cycles 0 # Number of idle cycles
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system.cpu0.num_busy_cycles 523247 # Number of busy cycles
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system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu0.idle_fraction 0 # Percentage of idle cycles
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system.cpu0.icache.replacements 215 # number of replacements
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system.cpu0.icache.tagsinuse 212.464540 # Cycle average of tags in use
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system.cpu0.icache.total_refs 157606 # Total number of references to valid blocks.
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system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks.
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system.cpu0.icache.avg_refs 337.486081 # Average number of references to valid blocks.
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system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu0.icache.occ_blocks::cpu0.inst 212.464540 # Average occupied blocks per requestor
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system.cpu0.icache.occ_percent::cpu0.inst 0.414970 # Average percentage of cache occupancy
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system.cpu0.icache.occ_percent::total 0.414970 # Average percentage of cache occupancy
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system.cpu0.icache.ReadReq_hits::cpu0.inst 157606 # number of ReadReq hits
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system.cpu0.icache.ReadReq_hits::total 157606 # number of ReadReq hits
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system.cpu0.icache.demand_hits::cpu0.inst 157606 # number of demand (read+write) hits
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system.cpu0.icache.demand_hits::total 157606 # number of demand (read+write) hits
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system.cpu0.icache.overall_hits::cpu0.inst 157606 # number of overall hits
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system.cpu0.icache.overall_hits::total 157606 # number of overall hits
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system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
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system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
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system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
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system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
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system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
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system.cpu0.icache.overall_misses::total 467 # number of overall misses
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system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18144000 # number of ReadReq miss cycles
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system.cpu0.icache.ReadReq_miss_latency::total 18144000 # number of ReadReq miss cycles
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system.cpu0.icache.demand_miss_latency::cpu0.inst 18144000 # number of demand (read+write) miss cycles
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system.cpu0.icache.demand_miss_latency::total 18144000 # number of demand (read+write) miss cycles
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system.cpu0.icache.overall_miss_latency::cpu0.inst 18144000 # number of overall miss cycles
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system.cpu0.icache.overall_miss_latency::total 18144000 # number of overall miss cycles
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system.cpu0.icache.ReadReq_accesses::cpu0.inst 158073 # number of ReadReq accesses(hits+misses)
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system.cpu0.icache.ReadReq_accesses::total 158073 # number of ReadReq accesses(hits+misses)
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system.cpu0.icache.demand_accesses::cpu0.inst 158073 # number of demand (read+write) accesses
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system.cpu0.icache.demand_accesses::total 158073 # number of demand (read+write) accesses
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system.cpu0.icache.overall_accesses::cpu0.inst 158073 # number of overall (read+write) accesses
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system.cpu0.icache.overall_accesses::total 158073 # number of overall (read+write) accesses
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system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002954 # miss rate for ReadReq accesses
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system.cpu0.icache.ReadReq_miss_rate::total 0.002954 # miss rate for ReadReq accesses
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system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002954 # miss rate for demand accesses
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system.cpu0.icache.demand_miss_rate::total 0.002954 # miss rate for demand accesses
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system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002954 # miss rate for overall accesses
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system.cpu0.icache.overall_miss_rate::total 0.002954 # miss rate for overall accesses
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system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38852.248394 # average ReadReq miss latency
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system.cpu0.icache.ReadReq_avg_miss_latency::total 38852.248394 # average ReadReq miss latency
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system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38852.248394 # average overall miss latency
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system.cpu0.icache.demand_avg_miss_latency::total 38852.248394 # average overall miss latency
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system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38852.248394 # average overall miss latency
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system.cpu0.icache.overall_avg_miss_latency::total 38852.248394 # average overall miss latency
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system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu0.icache.fast_writes 0 # number of fast writes performed
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system.cpu0.icache.cache_copies 0 # number of cache copies performed
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system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses
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system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses
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system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses
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system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses
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system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses
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system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses
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system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17210000 # number of ReadReq MSHR miss cycles
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system.cpu0.icache.ReadReq_mshr_miss_latency::total 17210000 # number of ReadReq MSHR miss cycles
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system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17210000 # number of demand (read+write) MSHR miss cycles
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system.cpu0.icache.demand_mshr_miss_latency::total 17210000 # number of demand (read+write) MSHR miss cycles
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system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17210000 # number of overall MSHR miss cycles
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system.cpu0.icache.overall_mshr_miss_latency::total 17210000 # number of overall MSHR miss cycles
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system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002954 # mshr miss rate for ReadReq accesses
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system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002954 # mshr miss rate for ReadReq accesses
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system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002954 # mshr miss rate for demand accesses
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system.cpu0.icache.demand_mshr_miss_rate::total 0.002954 # mshr miss rate for demand accesses
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system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002954 # mshr miss rate for overall accesses
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system.cpu0.icache.overall_mshr_miss_rate::total 0.002954 # mshr miss rate for overall accesses
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system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36852.248394 # average ReadReq mshr miss latency
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system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36852.248394 # average ReadReq mshr miss latency
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system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36852.248394 # average overall mshr miss latency
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system.cpu0.icache.demand_avg_mshr_miss_latency::total 36852.248394 # average overall mshr miss latency
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system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36852.248394 # average overall mshr miss latency
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system.cpu0.icache.overall_avg_mshr_miss_latency::total 36852.248394 # average overall mshr miss latency
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system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.dcache.replacements 2 # number of replacements
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system.cpu0.dcache.tagsinuse 145.601248 # Cycle average of tags in use
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system.cpu0.dcache.total_refs 73215 # Total number of references to valid blocks.
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system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks.
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system.cpu0.dcache.avg_refs 438.413174 # Average number of references to valid blocks.
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system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu0.dcache.occ_blocks::cpu0.data 145.601248 # Average occupied blocks per requestor
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system.cpu0.dcache.occ_percent::cpu0.data 0.284377 # Average percentage of cache occupancy
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system.cpu0.dcache.occ_percent::total 0.284377 # Average percentage of cache occupancy
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system.cpu0.dcache.ReadReq_hits::cpu0.data 48647 # number of ReadReq hits
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system.cpu0.dcache.ReadReq_hits::total 48647 # number of ReadReq hits
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system.cpu0.dcache.WriteReq_hits::cpu0.data 24686 # number of WriteReq hits
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system.cpu0.dcache.WriteReq_hits::total 24686 # number of WriteReq hits
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system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits
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system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits
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system.cpu0.dcache.demand_hits::cpu0.data 73333 # number of demand (read+write) hits
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system.cpu0.dcache.demand_hits::total 73333 # number of demand (read+write) hits
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system.cpu0.dcache.overall_hits::cpu0.data 73333 # number of overall hits
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system.cpu0.dcache.overall_hits::total 73333 # number of overall hits
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system.cpu0.dcache.ReadReq_misses::cpu0.data 162 # number of ReadReq misses
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system.cpu0.dcache.ReadReq_misses::total 162 # number of ReadReq misses
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system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses
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system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses
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system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses
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system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses
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system.cpu0.dcache.demand_misses::cpu0.data 345 # number of demand (read+write) misses
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system.cpu0.dcache.demand_misses::total 345 # number of demand (read+write) misses
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system.cpu0.dcache.overall_misses::cpu0.data 345 # number of overall misses
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system.cpu0.dcache.overall_misses::total 345 # number of overall misses
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system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4649500 # number of ReadReq miss cycles
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system.cpu0.dcache.ReadReq_miss_latency::total 4649500 # number of ReadReq miss cycles
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system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7005000 # number of WriteReq miss cycles
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system.cpu0.dcache.WriteReq_miss_latency::total 7005000 # number of WriteReq miss cycles
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system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 363500 # number of SwapReq miss cycles
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system.cpu0.dcache.SwapReq_miss_latency::total 363500 # number of SwapReq miss cycles
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system.cpu0.dcache.demand_miss_latency::cpu0.data 11654500 # number of demand (read+write) miss cycles
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system.cpu0.dcache.demand_miss_latency::total 11654500 # number of demand (read+write) miss cycles
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system.cpu0.dcache.overall_miss_latency::cpu0.data 11654500 # number of overall miss cycles
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system.cpu0.dcache.overall_miss_latency::total 11654500 # number of overall miss cycles
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system.cpu0.dcache.ReadReq_accesses::cpu0.data 48809 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.ReadReq_accesses::total 48809 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.WriteReq_accesses::cpu0.data 24869 # number of WriteReq accesses(hits+misses)
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system.cpu0.dcache.WriteReq_accesses::total 24869 # number of WriteReq accesses(hits+misses)
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system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
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system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
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system.cpu0.dcache.demand_accesses::cpu0.data 73678 # number of demand (read+write) accesses
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system.cpu0.dcache.demand_accesses::total 73678 # number of demand (read+write) accesses
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system.cpu0.dcache.overall_accesses::cpu0.data 73678 # number of overall (read+write) accesses
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system.cpu0.dcache.overall_accesses::total 73678 # number of overall (read+write) accesses
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system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003319 # miss rate for ReadReq accesses
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|
system.cpu0.dcache.ReadReq_miss_rate::total 0.003319 # miss rate for ReadReq accesses
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system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007359 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.007359 # miss rate for WriteReq accesses
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system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses
|
|
system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses
|
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system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004683 # miss rate for demand accesses
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system.cpu0.dcache.demand_miss_rate::total 0.004683 # miss rate for demand accesses
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system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004683 # miss rate for overall accesses
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system.cpu0.dcache.overall_miss_rate::total 0.004683 # miss rate for overall accesses
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system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28700.617284 # average ReadReq miss latency
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system.cpu0.dcache.ReadReq_avg_miss_latency::total 28700.617284 # average ReadReq miss latency
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system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38278.688525 # average WriteReq miss latency
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system.cpu0.dcache.WriteReq_avg_miss_latency::total 38278.688525 # average WriteReq miss latency
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system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13980.769231 # average SwapReq miss latency
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system.cpu0.dcache.SwapReq_avg_miss_latency::total 13980.769231 # average SwapReq miss latency
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system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33781.159420 # average overall miss latency
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system.cpu0.dcache.demand_avg_miss_latency::total 33781.159420 # average overall miss latency
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system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33781.159420 # average overall miss latency
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|
system.cpu0.dcache.overall_avg_miss_latency::total 33781.159420 # average overall miss latency
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
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system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
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system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 1 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 162 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses
|
|
system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 345 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 345 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4325500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4325500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6639000 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6639000 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 311500 # number of SwapReq MSHR miss cycles
|
|
system.cpu0.dcache.SwapReq_mshr_miss_latency::total 311500 # number of SwapReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10964500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 10964500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10964500 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 10964500 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003319 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003319 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007359 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007359 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses
|
|
system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004683 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.004683 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004683 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.004683 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26700.617284 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26700.617284 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36278.688525 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36278.688525 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11980.769231 # average SwapReq mshr miss latency
|
|
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11980.769231 # average SwapReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31781.159420 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31781.159420 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31781.159420 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31781.159420 # average overall mshr miss latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.numCycles 523247 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.committedInsts 173283 # Number of instructions committed
|
|
system.cpu1.committedOps 173283 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 108736 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 637 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 36284 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 108736 # number of integer instructions
|
|
system.cpu1.num_fp_insts 0 # number of float instructions
|
|
system.cpu1.num_int_register_reads 252002 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 93825 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
|
|
system.cpu1.num_mem_refs 48621 # number of memory refs
|
|
system.cpu1.num_load_insts 40031 # Number of load instructions
|
|
system.cpu1.num_store_insts 8590 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 68750.001737 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 454496.998263 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.868609 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.131391 # Percentage of idle cycles
|
|
system.cpu1.icache.replacements 280 # number of replacements
|
|
system.cpu1.icache.tagsinuse 65.593035 # Cycle average of tags in use
|
|
system.cpu1.icache.total_refs 172950 # Total number of references to valid blocks.
|
|
system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.avg_refs 472.540984 # Average number of references to valid blocks.
|
|
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.occ_blocks::cpu1.inst 65.593035 # Average occupied blocks per requestor
|
|
system.cpu1.icache.occ_percent::cpu1.inst 0.128111 # Average percentage of cache occupancy
|
|
system.cpu1.icache.occ_percent::total 0.128111 # Average percentage of cache occupancy
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 172950 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 172950 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 172950 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 172950 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 172950 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 172950 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 366 # number of overall misses
|
|
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5373500 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_latency::total 5373500 # number of ReadReq miss cycles
|
|
system.cpu1.icache.demand_miss_latency::cpu1.inst 5373500 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_latency::total 5373500 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.overall_miss_latency::cpu1.inst 5373500 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_latency::total 5373500 # number of overall miss cycles
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 173316 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 173316 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 173316 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 173316 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 173316 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 173316 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002112 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.002112 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002112 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.002112 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002112 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.002112 # miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14681.693989 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total 14681.693989 # average ReadReq miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14681.693989 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::total 14681.693989 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14681.693989 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::total 14681.693989 # average overall miss latency
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4641500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::total 4641500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4641500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::total 4641500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4641500 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::total 4641500 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002112 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002112 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002112 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::total 0.002112 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002112 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::total 0.002112 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12681.693989 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12681.693989 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12681.693989 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::total 12681.693989 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12681.693989 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::total 12681.693989 # average overall mshr miss latency
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dcache.replacements 0 # number of replacements
|
|
system.cpu1.dcache.tagsinuse 25.918058 # Cycle average of tags in use
|
|
system.cpu1.dcache.total_refs 19532 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.avg_refs 651.066667 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.occ_blocks::cpu1.data 25.918058 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.occ_percent::cpu1.data 0.050621 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.occ_percent::total 0.050621 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 39847 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 39847 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 8412 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 8412 # number of WriteReq hits
|
|
system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits
|
|
system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 48259 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 48259 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 48259 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 48259 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 177 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 177 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 105 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 105 # number of WriteReq misses
|
|
system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses
|
|
system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 282 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 282 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 282 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 282 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3316000 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_latency::total 3316000 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1875500 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::total 1875500 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 659500 # number of SwapReq miss cycles
|
|
system.cpu1.dcache.SwapReq_miss_latency::total 659500 # number of SwapReq miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::cpu1.data 5191500 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::total 5191500 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::cpu1.data 5191500 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::total 5191500 # number of overall miss cycles
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 40024 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 40024 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 8517 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 8517 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses)
|
|
system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 48541 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 48541 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 48541 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 48541 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004422 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.004422 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012328 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.012328 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.774648 # miss rate for SwapReq accesses
|
|
system.cpu1.dcache.SwapReq_miss_rate::total 0.774648 # miss rate for SwapReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005810 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.005810 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005810 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.005810 # miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18734.463277 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total 18734.463277 # average ReadReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17861.904762 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total 17861.904762 # average WriteReq miss latency
|
|
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 11990.909091 # average SwapReq miss latency
|
|
system.cpu1.dcache.SwapReq_avg_miss_latency::total 11990.909091 # average SwapReq miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18409.574468 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::total 18409.574468 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18409.574468 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::total 18409.574468 # average overall miss latency
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 177 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses
|
|
system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::cpu1.data 282 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::total 282 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 282 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::total 282 # number of overall MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2962000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2962000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1665500 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1665500 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 549500 # number of SwapReq MSHR miss cycles
|
|
system.cpu1.dcache.SwapReq_mshr_miss_latency::total 549500 # number of SwapReq MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4627500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::total 4627500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4627500 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::total 4627500 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004422 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004422 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012328 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.012328 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.774648 # mshr miss rate for SwapReq accesses
|
|
system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.774648 # mshr miss rate for SwapReq accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005810 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total 0.005810 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005810 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total 0.005810 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16734.463277 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16734.463277 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15861.904762 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15861.904762 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 9990.909091 # average SwapReq mshr miss latency
|
|
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 9990.909091 # average SwapReq mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16409.574468 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16409.574468 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16409.574468 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16409.574468 # average overall mshr miss latency
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.numCycles 523246 # number of cpu cycles simulated
|
|
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu2.committedInsts 160665 # Number of instructions committed
|
|
system.cpu2.committedOps 160665 # Number of ops (including micro ops) committed
|
|
system.cpu2.num_int_alu_accesses 113639 # Number of integer alu accesses
|
|
system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses
|
|
system.cpu2.num_func_calls 637 # number of times a function call or return occured
|
|
system.cpu2.num_conditional_control_insts 27518 # number of instructions that are conditional controls
|
|
system.cpu2.num_int_insts 113639 # number of integer instructions
|
|
system.cpu2.num_fp_insts 0 # number of float instructions
|
|
system.cpu2.num_int_register_reads 306682 # number of times the integer registers were read
|
|
system.cpu2.num_int_register_writes 118721 # number of times the integer registers were written
|
|
system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read
|
|
system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written
|
|
system.cpu2.num_mem_refs 62290 # number of memory refs
|
|
system.cpu2.num_load_insts 42488 # Number of load instructions
|
|
system.cpu2.num_store_insts 19802 # Number of store instructions
|
|
system.cpu2.num_idle_cycles 69015.869837 # Number of idle cycles
|
|
system.cpu2.num_busy_cycles 454230.130163 # Number of busy cycles
|
|
system.cpu2.not_idle_fraction 0.868101 # Percentage of non-idle cycles
|
|
system.cpu2.idle_fraction 0.131899 # Percentage of idle cycles
|
|
system.cpu2.icache.replacements 281 # number of replacements
|
|
system.cpu2.icache.tagsinuse 67.731754 # Cycle average of tags in use
|
|
system.cpu2.icache.total_refs 160331 # Total number of references to valid blocks.
|
|
system.cpu2.icache.sampled_refs 367 # Sample count of references to valid blocks.
|
|
system.cpu2.icache.avg_refs 436.869210 # Average number of references to valid blocks.
|
|
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu2.icache.occ_blocks::cpu2.inst 67.731754 # Average occupied blocks per requestor
|
|
system.cpu2.icache.occ_percent::cpu2.inst 0.132289 # Average percentage of cache occupancy
|
|
system.cpu2.icache.occ_percent::total 0.132289 # Average percentage of cache occupancy
|
|
system.cpu2.icache.ReadReq_hits::cpu2.inst 160331 # number of ReadReq hits
|
|
system.cpu2.icache.ReadReq_hits::total 160331 # number of ReadReq hits
|
|
system.cpu2.icache.demand_hits::cpu2.inst 160331 # number of demand (read+write) hits
|
|
system.cpu2.icache.demand_hits::total 160331 # number of demand (read+write) hits
|
|
system.cpu2.icache.overall_hits::cpu2.inst 160331 # number of overall hits
|
|
system.cpu2.icache.overall_hits::total 160331 # number of overall hits
|
|
system.cpu2.icache.ReadReq_misses::cpu2.inst 367 # number of ReadReq misses
|
|
system.cpu2.icache.ReadReq_misses::total 367 # number of ReadReq misses
|
|
system.cpu2.icache.demand_misses::cpu2.inst 367 # number of demand (read+write) misses
|
|
system.cpu2.icache.demand_misses::total 367 # number of demand (read+write) misses
|
|
system.cpu2.icache.overall_misses::cpu2.inst 367 # number of overall misses
|
|
system.cpu2.icache.overall_misses::total 367 # number of overall misses
|
|
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5321500 # number of ReadReq miss cycles
|
|
system.cpu2.icache.ReadReq_miss_latency::total 5321500 # number of ReadReq miss cycles
|
|
system.cpu2.icache.demand_miss_latency::cpu2.inst 5321500 # number of demand (read+write) miss cycles
|
|
system.cpu2.icache.demand_miss_latency::total 5321500 # number of demand (read+write) miss cycles
|
|
system.cpu2.icache.overall_miss_latency::cpu2.inst 5321500 # number of overall miss cycles
|
|
system.cpu2.icache.overall_miss_latency::total 5321500 # number of overall miss cycles
|
|
system.cpu2.icache.ReadReq_accesses::cpu2.inst 160698 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.icache.ReadReq_accesses::total 160698 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.icache.demand_accesses::cpu2.inst 160698 # number of demand (read+write) accesses
|
|
system.cpu2.icache.demand_accesses::total 160698 # number of demand (read+write) accesses
|
|
system.cpu2.icache.overall_accesses::cpu2.inst 160698 # number of overall (read+write) accesses
|
|
system.cpu2.icache.overall_accesses::total 160698 # number of overall (read+write) accesses
|
|
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002284 # miss rate for ReadReq accesses
|
|
system.cpu2.icache.ReadReq_miss_rate::total 0.002284 # miss rate for ReadReq accesses
|
|
system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002284 # miss rate for demand accesses
|
|
system.cpu2.icache.demand_miss_rate::total 0.002284 # miss rate for demand accesses
|
|
system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002284 # miss rate for overall accesses
|
|
system.cpu2.icache.overall_miss_rate::total 0.002284 # miss rate for overall accesses
|
|
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14500 # average ReadReq miss latency
|
|
system.cpu2.icache.ReadReq_avg_miss_latency::total 14500 # average ReadReq miss latency
|
|
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14500 # average overall miss latency
|
|
system.cpu2.icache.demand_avg_miss_latency::total 14500 # average overall miss latency
|
|
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14500 # average overall miss latency
|
|
system.cpu2.icache.overall_avg_miss_latency::total 14500 # average overall miss latency
|
|
system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu2.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu2.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 367 # number of ReadReq MSHR misses
|
|
system.cpu2.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses
|
|
system.cpu2.icache.demand_mshr_misses::cpu2.inst 367 # number of demand (read+write) MSHR misses
|
|
system.cpu2.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses
|
|
system.cpu2.icache.overall_mshr_misses::cpu2.inst 367 # number of overall MSHR misses
|
|
system.cpu2.icache.overall_mshr_misses::total 367 # number of overall MSHR misses
|
|
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4587500 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.icache.ReadReq_mshr_miss_latency::total 4587500 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4587500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.icache.demand_mshr_miss_latency::total 4587500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4587500 # number of overall MSHR miss cycles
|
|
system.cpu2.icache.overall_mshr_miss_latency::total 4587500 # number of overall MSHR miss cycles
|
|
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002284 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002284 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002284 # mshr miss rate for demand accesses
|
|
system.cpu2.icache.demand_mshr_miss_rate::total 0.002284 # mshr miss rate for demand accesses
|
|
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002284 # mshr miss rate for overall accesses
|
|
system.cpu2.icache.overall_mshr_miss_rate::total 0.002284 # mshr miss rate for overall accesses
|
|
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12500 # average ReadReq mshr miss latency
|
|
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12500 # average ReadReq mshr miss latency
|
|
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12500 # average overall mshr miss latency
|
|
system.cpu2.icache.demand_avg_mshr_miss_latency::total 12500 # average overall mshr miss latency
|
|
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12500 # average overall mshr miss latency
|
|
system.cpu2.icache.overall_avg_mshr_miss_latency::total 12500 # average overall mshr miss latency
|
|
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.dcache.replacements 0 # number of replacements
|
|
system.cpu2.dcache.tagsinuse 26.833050 # Cycle average of tags in use
|
|
system.cpu2.dcache.total_refs 41851 # Total number of references to valid blocks.
|
|
system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks.
|
|
system.cpu2.dcache.avg_refs 1443.137931 # Average number of references to valid blocks.
|
|
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu2.dcache.occ_blocks::cpu2.data 26.833050 # Average occupied blocks per requestor
|
|
system.cpu2.dcache.occ_percent::cpu2.data 0.052408 # Average percentage of cache occupancy
|
|
system.cpu2.dcache.occ_percent::total 0.052408 # Average percentage of cache occupancy
|
|
system.cpu2.dcache.ReadReq_hits::cpu2.data 42328 # number of ReadReq hits
|
|
system.cpu2.dcache.ReadReq_hits::total 42328 # number of ReadReq hits
|
|
system.cpu2.dcache.WriteReq_hits::cpu2.data 19626 # number of WriteReq hits
|
|
system.cpu2.dcache.WriteReq_hits::total 19626 # number of WriteReq hits
|
|
system.cpu2.dcache.SwapReq_hits::cpu2.data 10 # number of SwapReq hits
|
|
system.cpu2.dcache.SwapReq_hits::total 10 # number of SwapReq hits
|
|
system.cpu2.dcache.demand_hits::cpu2.data 61954 # number of demand (read+write) hits
|
|
system.cpu2.dcache.demand_hits::total 61954 # number of demand (read+write) hits
|
|
system.cpu2.dcache.overall_hits::cpu2.data 61954 # number of overall hits
|
|
system.cpu2.dcache.overall_hits::total 61954 # number of overall hits
|
|
system.cpu2.dcache.ReadReq_misses::cpu2.data 152 # number of ReadReq misses
|
|
system.cpu2.dcache.ReadReq_misses::total 152 # number of ReadReq misses
|
|
system.cpu2.dcache.WriteReq_misses::cpu2.data 106 # number of WriteReq misses
|
|
system.cpu2.dcache.WriteReq_misses::total 106 # number of WriteReq misses
|
|
system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses
|
|
system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses
|
|
system.cpu2.dcache.demand_misses::cpu2.data 258 # number of demand (read+write) misses
|
|
system.cpu2.dcache.demand_misses::total 258 # number of demand (read+write) misses
|
|
system.cpu2.dcache.overall_misses::cpu2.data 258 # number of overall misses
|
|
system.cpu2.dcache.overall_misses::total 258 # number of overall misses
|
|
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 1938000 # number of ReadReq miss cycles
|
|
system.cpu2.dcache.ReadReq_miss_latency::total 1938000 # number of ReadReq miss cycles
|
|
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2155000 # number of WriteReq miss cycles
|
|
system.cpu2.dcache.WriteReq_miss_latency::total 2155000 # number of WriteReq miss cycles
|
|
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 612500 # number of SwapReq miss cycles
|
|
system.cpu2.dcache.SwapReq_miss_latency::total 612500 # number of SwapReq miss cycles
|
|
system.cpu2.dcache.demand_miss_latency::cpu2.data 4093000 # number of demand (read+write) miss cycles
|
|
system.cpu2.dcache.demand_miss_latency::total 4093000 # number of demand (read+write) miss cycles
|
|
system.cpu2.dcache.overall_miss_latency::cpu2.data 4093000 # number of overall miss cycles
|
|
system.cpu2.dcache.overall_miss_latency::total 4093000 # number of overall miss cycles
|
|
system.cpu2.dcache.ReadReq_accesses::cpu2.data 42480 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.dcache.ReadReq_accesses::total 42480 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.dcache.WriteReq_accesses::cpu2.data 19732 # number of WriteReq accesses(hits+misses)
|
|
system.cpu2.dcache.WriteReq_accesses::total 19732 # number of WriteReq accesses(hits+misses)
|
|
system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses)
|
|
system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses)
|
|
system.cpu2.dcache.demand_accesses::cpu2.data 62212 # number of demand (read+write) accesses
|
|
system.cpu2.dcache.demand_accesses::total 62212 # number of demand (read+write) accesses
|
|
system.cpu2.dcache.overall_accesses::cpu2.data 62212 # number of overall (read+write) accesses
|
|
system.cpu2.dcache.overall_accesses::total 62212 # number of overall (read+write) accesses
|
|
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003578 # miss rate for ReadReq accesses
|
|
system.cpu2.dcache.ReadReq_miss_rate::total 0.003578 # miss rate for ReadReq accesses
|
|
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.005372 # miss rate for WriteReq accesses
|
|
system.cpu2.dcache.WriteReq_miss_rate::total 0.005372 # miss rate for WriteReq accesses
|
|
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.852941 # miss rate for SwapReq accesses
|
|
system.cpu2.dcache.SwapReq_miss_rate::total 0.852941 # miss rate for SwapReq accesses
|
|
system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004147 # miss rate for demand accesses
|
|
system.cpu2.dcache.demand_miss_rate::total 0.004147 # miss rate for demand accesses
|
|
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004147 # miss rate for overall accesses
|
|
system.cpu2.dcache.overall_miss_rate::total 0.004147 # miss rate for overall accesses
|
|
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 12750 # average ReadReq miss latency
|
|
system.cpu2.dcache.ReadReq_avg_miss_latency::total 12750 # average ReadReq miss latency
|
|
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20330.188679 # average WriteReq miss latency
|
|
system.cpu2.dcache.WriteReq_avg_miss_latency::total 20330.188679 # average WriteReq miss latency
|
|
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10560.344828 # average SwapReq miss latency
|
|
system.cpu2.dcache.SwapReq_avg_miss_latency::total 10560.344828 # average SwapReq miss latency
|
|
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15864.341085 # average overall miss latency
|
|
system.cpu2.dcache.demand_avg_miss_latency::total 15864.341085 # average overall miss latency
|
|
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15864.341085 # average overall miss latency
|
|
system.cpu2.dcache.overall_avg_miss_latency::total 15864.341085 # average overall miss latency
|
|
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 152 # number of ReadReq MSHR misses
|
|
system.cpu2.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses
|
|
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses
|
|
system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses
|
|
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses
|
|
system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses
|
|
system.cpu2.dcache.demand_mshr_misses::cpu2.data 258 # number of demand (read+write) MSHR misses
|
|
system.cpu2.dcache.demand_mshr_misses::total 258 # number of demand (read+write) MSHR misses
|
|
system.cpu2.dcache.overall_mshr_misses::cpu2.data 258 # number of overall MSHR misses
|
|
system.cpu2.dcache.overall_mshr_misses::total 258 # number of overall MSHR misses
|
|
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1634000 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1634000 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1943000 # number of WriteReq MSHR miss cycles
|
|
system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1943000 # number of WriteReq MSHR miss cycles
|
|
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 496500 # number of SwapReq MSHR miss cycles
|
|
system.cpu2.dcache.SwapReq_mshr_miss_latency::total 496500 # number of SwapReq MSHR miss cycles
|
|
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3577000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.dcache.demand_mshr_miss_latency::total 3577000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3577000 # number of overall MSHR miss cycles
|
|
system.cpu2.dcache.overall_mshr_miss_latency::total 3577000 # number of overall MSHR miss cycles
|
|
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003578 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003578 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.005372 # mshr miss rate for WriteReq accesses
|
|
system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.005372 # mshr miss rate for WriteReq accesses
|
|
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.852941 # mshr miss rate for SwapReq accesses
|
|
system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.852941 # mshr miss rate for SwapReq accesses
|
|
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004147 # mshr miss rate for demand accesses
|
|
system.cpu2.dcache.demand_mshr_miss_rate::total 0.004147 # mshr miss rate for demand accesses
|
|
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004147 # mshr miss rate for overall accesses
|
|
system.cpu2.dcache.overall_mshr_miss_rate::total 0.004147 # mshr miss rate for overall accesses
|
|
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10750 # average ReadReq mshr miss latency
|
|
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10750 # average ReadReq mshr miss latency
|
|
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 18330.188679 # average WriteReq mshr miss latency
|
|
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 18330.188679 # average WriteReq mshr miss latency
|
|
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8560.344828 # average SwapReq mshr miss latency
|
|
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8560.344828 # average SwapReq mshr miss latency
|
|
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13864.341085 # average overall mshr miss latency
|
|
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13864.341085 # average overall mshr miss latency
|
|
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13864.341085 # average overall mshr miss latency
|
|
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13864.341085 # average overall mshr miss latency
|
|
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu3.numCycles 523246 # number of cpu cycles simulated
|
|
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu3.committedInsts 168281 # Number of instructions committed
|
|
system.cpu3.committedOps 168281 # Number of ops (including micro ops) committed
|
|
system.cpu3.num_int_alu_accesses 108796 # Number of integer alu accesses
|
|
system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses
|
|
system.cpu3.num_func_calls 637 # number of times a function call or return occured
|
|
system.cpu3.num_conditional_control_insts 33752 # number of instructions that are conditional controls
|
|
system.cpu3.num_int_insts 108796 # number of integer instructions
|
|
system.cpu3.num_fp_insts 0 # number of float instructions
|
|
system.cpu3.num_int_register_reads 262371 # number of times the integer registers were read
|
|
system.cpu3.num_int_register_writes 98980 # number of times the integer registers were written
|
|
system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read
|
|
system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written
|
|
system.cpu3.num_mem_refs 51213 # number of memory refs
|
|
system.cpu3.num_load_insts 40064 # Number of load instructions
|
|
system.cpu3.num_store_insts 11149 # Number of store instructions
|
|
system.cpu3.num_idle_cycles 69253.869381 # Number of idle cycles
|
|
system.cpu3.num_busy_cycles 453992.130619 # Number of busy cycles
|
|
system.cpu3.not_idle_fraction 0.867646 # Percentage of non-idle cycles
|
|
system.cpu3.idle_fraction 0.132354 # Percentage of idle cycles
|
|
system.cpu3.icache.replacements 280 # number of replacements
|
|
system.cpu3.icache.tagsinuse 70.063196 # Cycle average of tags in use
|
|
system.cpu3.icache.total_refs 167948 # Total number of references to valid blocks.
|
|
system.cpu3.icache.sampled_refs 366 # Sample count of references to valid blocks.
|
|
system.cpu3.icache.avg_refs 458.874317 # Average number of references to valid blocks.
|
|
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu3.icache.occ_blocks::cpu3.inst 70.063196 # Average occupied blocks per requestor
|
|
system.cpu3.icache.occ_percent::cpu3.inst 0.136842 # Average percentage of cache occupancy
|
|
system.cpu3.icache.occ_percent::total 0.136842 # Average percentage of cache occupancy
|
|
system.cpu3.icache.ReadReq_hits::cpu3.inst 167948 # number of ReadReq hits
|
|
system.cpu3.icache.ReadReq_hits::total 167948 # number of ReadReq hits
|
|
system.cpu3.icache.demand_hits::cpu3.inst 167948 # number of demand (read+write) hits
|
|
system.cpu3.icache.demand_hits::total 167948 # number of demand (read+write) hits
|
|
system.cpu3.icache.overall_hits::cpu3.inst 167948 # number of overall hits
|
|
system.cpu3.icache.overall_hits::total 167948 # number of overall hits
|
|
system.cpu3.icache.ReadReq_misses::cpu3.inst 366 # number of ReadReq misses
|
|
system.cpu3.icache.ReadReq_misses::total 366 # number of ReadReq misses
|
|
system.cpu3.icache.demand_misses::cpu3.inst 366 # number of demand (read+write) misses
|
|
system.cpu3.icache.demand_misses::total 366 # number of demand (read+write) misses
|
|
system.cpu3.icache.overall_misses::cpu3.inst 366 # number of overall misses
|
|
system.cpu3.icache.overall_misses::total 366 # number of overall misses
|
|
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7343000 # number of ReadReq miss cycles
|
|
system.cpu3.icache.ReadReq_miss_latency::total 7343000 # number of ReadReq miss cycles
|
|
system.cpu3.icache.demand_miss_latency::cpu3.inst 7343000 # number of demand (read+write) miss cycles
|
|
system.cpu3.icache.demand_miss_latency::total 7343000 # number of demand (read+write) miss cycles
|
|
system.cpu3.icache.overall_miss_latency::cpu3.inst 7343000 # number of overall miss cycles
|
|
system.cpu3.icache.overall_miss_latency::total 7343000 # number of overall miss cycles
|
|
system.cpu3.icache.ReadReq_accesses::cpu3.inst 168314 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.icache.ReadReq_accesses::total 168314 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.icache.demand_accesses::cpu3.inst 168314 # number of demand (read+write) accesses
|
|
system.cpu3.icache.demand_accesses::total 168314 # number of demand (read+write) accesses
|
|
system.cpu3.icache.overall_accesses::cpu3.inst 168314 # number of overall (read+write) accesses
|
|
system.cpu3.icache.overall_accesses::total 168314 # number of overall (read+write) accesses
|
|
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002175 # miss rate for ReadReq accesses
|
|
system.cpu3.icache.ReadReq_miss_rate::total 0.002175 # miss rate for ReadReq accesses
|
|
system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002175 # miss rate for demand accesses
|
|
system.cpu3.icache.demand_miss_rate::total 0.002175 # miss rate for demand accesses
|
|
system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002175 # miss rate for overall accesses
|
|
system.cpu3.icache.overall_miss_rate::total 0.002175 # miss rate for overall accesses
|
|
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 20062.841530 # average ReadReq miss latency
|
|
system.cpu3.icache.ReadReq_avg_miss_latency::total 20062.841530 # average ReadReq miss latency
|
|
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 20062.841530 # average overall miss latency
|
|
system.cpu3.icache.demand_avg_miss_latency::total 20062.841530 # average overall miss latency
|
|
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 20062.841530 # average overall miss latency
|
|
system.cpu3.icache.overall_avg_miss_latency::total 20062.841530 # average overall miss latency
|
|
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu3.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu3.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 366 # number of ReadReq MSHR misses
|
|
system.cpu3.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses
|
|
system.cpu3.icache.demand_mshr_misses::cpu3.inst 366 # number of demand (read+write) MSHR misses
|
|
system.cpu3.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
|
|
system.cpu3.icache.overall_mshr_misses::cpu3.inst 366 # number of overall MSHR misses
|
|
system.cpu3.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
|
|
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6611000 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.icache.ReadReq_mshr_miss_latency::total 6611000 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6611000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.icache.demand_mshr_miss_latency::total 6611000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6611000 # number of overall MSHR miss cycles
|
|
system.cpu3.icache.overall_mshr_miss_latency::total 6611000 # number of overall MSHR miss cycles
|
|
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002175 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002175 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002175 # mshr miss rate for demand accesses
|
|
system.cpu3.icache.demand_mshr_miss_rate::total 0.002175 # mshr miss rate for demand accesses
|
|
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002175 # mshr miss rate for overall accesses
|
|
system.cpu3.icache.overall_mshr_miss_rate::total 0.002175 # mshr miss rate for overall accesses
|
|
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 18062.841530 # average ReadReq mshr miss latency
|
|
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 18062.841530 # average ReadReq mshr miss latency
|
|
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 18062.841530 # average overall mshr miss latency
|
|
system.cpu3.icache.demand_avg_mshr_miss_latency::total 18062.841530 # average overall mshr miss latency
|
|
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 18062.841530 # average overall mshr miss latency
|
|
system.cpu3.icache.overall_avg_mshr_miss_latency::total 18062.841530 # average overall mshr miss latency
|
|
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu3.dcache.replacements 0 # number of replacements
|
|
system.cpu3.dcache.tagsinuse 27.713697 # Cycle average of tags in use
|
|
system.cpu3.dcache.total_refs 24536 # Total number of references to valid blocks.
|
|
system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks.
|
|
system.cpu3.dcache.avg_refs 846.068966 # Average number of references to valid blocks.
|
|
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu3.dcache.occ_blocks::cpu3.data 27.713697 # Average occupied blocks per requestor
|
|
system.cpu3.dcache.occ_percent::cpu3.data 0.054128 # Average percentage of cache occupancy
|
|
system.cpu3.dcache.occ_percent::total 0.054128 # Average percentage of cache occupancy
|
|
system.cpu3.dcache.ReadReq_hits::cpu3.data 39885 # number of ReadReq hits
|
|
system.cpu3.dcache.ReadReq_hits::total 39885 # number of ReadReq hits
|
|
system.cpu3.dcache.WriteReq_hits::cpu3.data 10974 # number of WriteReq hits
|
|
system.cpu3.dcache.WriteReq_hits::total 10974 # number of WriteReq hits
|
|
system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits
|
|
system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits
|
|
system.cpu3.dcache.demand_hits::cpu3.data 50859 # number of demand (read+write) hits
|
|
system.cpu3.dcache.demand_hits::total 50859 # number of demand (read+write) hits
|
|
system.cpu3.dcache.overall_hits::cpu3.data 50859 # number of overall hits
|
|
system.cpu3.dcache.overall_hits::total 50859 # number of overall hits
|
|
system.cpu3.dcache.ReadReq_misses::cpu3.data 172 # number of ReadReq misses
|
|
system.cpu3.dcache.ReadReq_misses::total 172 # number of ReadReq misses
|
|
system.cpu3.dcache.WriteReq_misses::cpu3.data 104 # number of WriteReq misses
|
|
system.cpu3.dcache.WriteReq_misses::total 104 # number of WriteReq misses
|
|
system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses
|
|
system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses
|
|
system.cpu3.dcache.demand_misses::cpu3.data 276 # number of demand (read+write) misses
|
|
system.cpu3.dcache.demand_misses::total 276 # number of demand (read+write) misses
|
|
system.cpu3.dcache.overall_misses::cpu3.data 276 # number of overall misses
|
|
system.cpu3.dcache.overall_misses::total 276 # number of overall misses
|
|
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3405000 # number of ReadReq miss cycles
|
|
system.cpu3.dcache.ReadReq_miss_latency::total 3405000 # number of ReadReq miss cycles
|
|
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1971500 # number of WriteReq miss cycles
|
|
system.cpu3.dcache.WriteReq_miss_latency::total 1971500 # number of WriteReq miss cycles
|
|
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 653500 # number of SwapReq miss cycles
|
|
system.cpu3.dcache.SwapReq_miss_latency::total 653500 # number of SwapReq miss cycles
|
|
system.cpu3.dcache.demand_miss_latency::cpu3.data 5376500 # number of demand (read+write) miss cycles
|
|
system.cpu3.dcache.demand_miss_latency::total 5376500 # number of demand (read+write) miss cycles
|
|
system.cpu3.dcache.overall_miss_latency::cpu3.data 5376500 # number of overall miss cycles
|
|
system.cpu3.dcache.overall_miss_latency::total 5376500 # number of overall miss cycles
|
|
system.cpu3.dcache.ReadReq_accesses::cpu3.data 40057 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.dcache.ReadReq_accesses::total 40057 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.dcache.WriteReq_accesses::cpu3.data 11078 # number of WriteReq accesses(hits+misses)
|
|
system.cpu3.dcache.WriteReq_accesses::total 11078 # number of WriteReq accesses(hits+misses)
|
|
system.cpu3.dcache.SwapReq_accesses::cpu3.data 69 # number of SwapReq accesses(hits+misses)
|
|
system.cpu3.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses)
|
|
system.cpu3.dcache.demand_accesses::cpu3.data 51135 # number of demand (read+write) accesses
|
|
system.cpu3.dcache.demand_accesses::total 51135 # number of demand (read+write) accesses
|
|
system.cpu3.dcache.overall_accesses::cpu3.data 51135 # number of overall (read+write) accesses
|
|
system.cpu3.dcache.overall_accesses::total 51135 # number of overall (read+write) accesses
|
|
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004294 # miss rate for ReadReq accesses
|
|
system.cpu3.dcache.ReadReq_miss_rate::total 0.004294 # miss rate for ReadReq accesses
|
|
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.009388 # miss rate for WriteReq accesses
|
|
system.cpu3.dcache.WriteReq_miss_rate::total 0.009388 # miss rate for WriteReq accesses
|
|
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.797101 # miss rate for SwapReq accesses
|
|
system.cpu3.dcache.SwapReq_miss_rate::total 0.797101 # miss rate for SwapReq accesses
|
|
system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005397 # miss rate for demand accesses
|
|
system.cpu3.dcache.demand_miss_rate::total 0.005397 # miss rate for demand accesses
|
|
system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005397 # miss rate for overall accesses
|
|
system.cpu3.dcache.overall_miss_rate::total 0.005397 # miss rate for overall accesses
|
|
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 19796.511628 # average ReadReq miss latency
|
|
system.cpu3.dcache.ReadReq_avg_miss_latency::total 19796.511628 # average ReadReq miss latency
|
|
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18956.730769 # average WriteReq miss latency
|
|
system.cpu3.dcache.WriteReq_avg_miss_latency::total 18956.730769 # average WriteReq miss latency
|
|
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 11881.818182 # average SwapReq miss latency
|
|
system.cpu3.dcache.SwapReq_avg_miss_latency::total 11881.818182 # average SwapReq miss latency
|
|
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 19480.072464 # average overall miss latency
|
|
system.cpu3.dcache.demand_avg_miss_latency::total 19480.072464 # average overall miss latency
|
|
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 19480.072464 # average overall miss latency
|
|
system.cpu3.dcache.overall_avg_miss_latency::total 19480.072464 # average overall miss latency
|
|
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 172 # number of ReadReq MSHR misses
|
|
system.cpu3.dcache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses
|
|
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 104 # number of WriteReq MSHR misses
|
|
system.cpu3.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses
|
|
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 55 # number of SwapReq MSHR misses
|
|
system.cpu3.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses
|
|
system.cpu3.dcache.demand_mshr_misses::cpu3.data 276 # number of demand (read+write) MSHR misses
|
|
system.cpu3.dcache.demand_mshr_misses::total 276 # number of demand (read+write) MSHR misses
|
|
system.cpu3.dcache.overall_mshr_misses::cpu3.data 276 # number of overall MSHR misses
|
|
system.cpu3.dcache.overall_mshr_misses::total 276 # number of overall MSHR misses
|
|
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 3061000 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.dcache.ReadReq_mshr_miss_latency::total 3061000 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1763500 # number of WriteReq MSHR miss cycles
|
|
system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1763500 # number of WriteReq MSHR miss cycles
|
|
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 543500 # number of SwapReq MSHR miss cycles
|
|
system.cpu3.dcache.SwapReq_mshr_miss_latency::total 543500 # number of SwapReq MSHR miss cycles
|
|
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4824500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.dcache.demand_mshr_miss_latency::total 4824500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4824500 # number of overall MSHR miss cycles
|
|
system.cpu3.dcache.overall_mshr_miss_latency::total 4824500 # number of overall MSHR miss cycles
|
|
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004294 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004294 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.009388 # mshr miss rate for WriteReq accesses
|
|
system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.009388 # mshr miss rate for WriteReq accesses
|
|
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.797101 # mshr miss rate for SwapReq accesses
|
|
system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.797101 # mshr miss rate for SwapReq accesses
|
|
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005397 # mshr miss rate for demand accesses
|
|
system.cpu3.dcache.demand_mshr_miss_rate::total 0.005397 # mshr miss rate for demand accesses
|
|
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005397 # mshr miss rate for overall accesses
|
|
system.cpu3.dcache.overall_mshr_miss_rate::total 0.005397 # mshr miss rate for overall accesses
|
|
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17796.511628 # average ReadReq mshr miss latency
|
|
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 17796.511628 # average ReadReq mshr miss latency
|
|
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 16956.730769 # average WriteReq mshr miss latency
|
|
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 16956.730769 # average WriteReq mshr miss latency
|
|
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 9881.818182 # average SwapReq mshr miss latency
|
|
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 9881.818182 # average SwapReq mshr miss latency
|
|
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 17480.072464 # average overall mshr miss latency
|
|
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 17480.072464 # average overall mshr miss latency
|
|
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 17480.072464 # average overall mshr miss latency
|
|
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 17480.072464 # average overall mshr miss latency
|
|
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.replacements 0 # number of replacements
|
|
system.l2c.tagsinuse 349.154335 # Cycle average of tags in use
|
|
system.l2c.total_refs 1221 # Total number of references to valid blocks.
|
|
system.l2c.sampled_refs 429 # Sample count of references to valid blocks.
|
|
system.l2c.avg_refs 2.846154 # Average number of references to valid blocks.
|
|
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.occ_blocks::writebacks 0.889459 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu0.inst 231.842883 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu0.data 54.217473 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu1.inst 6.219466 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu1.data 0.812784 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu2.inst 1.917796 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu2.data 0.863537 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu3.inst 46.262373 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu3.data 6.128563 # Average occupied blocks per requestor
|
|
system.l2c.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu0.inst 0.003538 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu1.inst 0.000095 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu1.data 0.000012 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu3.inst 0.000706 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu3.data 0.000094 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::total 0.005328 # Average percentage of cache occupancy
|
|
system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 352 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.inst 355 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu3.inst 306 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu3.data 3 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 1221 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 1 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits
|
|
system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 352 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu3.inst 306 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu3.data 3 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1221 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.inst 182 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 5 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 352 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 9 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.inst 355 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.data 9 # number of overall hits
|
|
system.l2c.overall_hits::cpu3.inst 306 # number of overall hits
|
|
system.l2c.overall_hits::cpu3.data 3 # number of overall hits
|
|
system.l2c.overall_hits::total 1221 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.inst 285 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.inst 14 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.data 2 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.inst 12 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.data 2 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu3.inst 60 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu3.data 8 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 449 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu2.data 20 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 85 # number of UpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu2.data 14 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu3.data 15 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses
|
|
system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 14 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 16 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.inst 12 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.data 16 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu3.inst 60 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu3.data 23 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 591 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.inst 285 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 165 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 14 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 16 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.inst 12 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.data 16 # number of overall misses
|
|
system.l2c.overall_misses::cpu3.inst 60 # number of overall misses
|
|
system.l2c.overall_misses::cpu3.data 23 # number of overall misses
|
|
system.l2c.overall_misses::total 591 # number of overall misses
|
|
system.l2c.ReadReq_miss_latency::cpu0.inst 14917500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.data 3451000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.inst 697500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.data 100000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu2.inst 601000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu2.data 104500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu3.inst 3071500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu3.data 410000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::total 23353000 # number of ReadReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 5169500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 736000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu2.data 737500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu3.data 793500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 7436500 # number of ReadExReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 14917500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 8620500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 697500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 836000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.inst 601000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.data 842000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu3.inst 3071500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu3.data 1203500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 30789500 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 14917500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 8620500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 697500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 836000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.inst 601000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.data 842000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu3.inst 3071500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu3.data 1203500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 30789500 # number of overall miss cycles
|
|
system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.data 11 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu2.inst 367 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu2.data 11 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu3.inst 366 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu3.data 11 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 87 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 14 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu2.data 14 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu3.data 15 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.inst 367 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu3.inst 366 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu3.data 26 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.inst 367 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu3.inst 366 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu3.data 26 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.inst 0.038251 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.data 0.181818 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu2.inst 0.032698 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu2.data 0.181818 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu3.inst 0.163934 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu3.data 0.727273 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::total 0.268862 # miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.977011 # miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.038251 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.640000 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.inst 0.032698 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.data 0.640000 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu3.inst 0.163934 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu3.data 0.884615 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.326159 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.038251 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.640000 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.inst 0.032698 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.data 0.640000 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu3.inst 0.163934 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu3.data 0.884615 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.326159 # miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52342.105263 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52287.878788 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49821.428571 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.data 50000 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 50083.333333 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu2.data 52250 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu3.inst 51191.666667 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu3.data 51250 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::total 52011.135857 # average ReadReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52217.171717 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52571.428571 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52678.571429 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52900 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 52369.718310 # average ReadExReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.inst 52342.105263 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.data 52245.454545 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 49821.428571 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 52250 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.inst 50083.333333 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.data 52625 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu3.inst 51191.666667 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu3.data 52326.086957 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 52097.292724 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.inst 52342.105263 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.data 52245.454545 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 49821.428571 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 52250 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.inst 50083.333333 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.data 52625 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu3.inst 51191.666667 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu3.data 52326.086957 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 52097.292724 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu2.inst 3 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu3.inst 7 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu3.data 1 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::total 19 # number of ReadReq MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu2.inst 3 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu3.inst 7 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu3.data 1 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::total 19 # number of demand (read+write) MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu2.inst 3 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu3.inst 7 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu3.data 1 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::total 19 # number of overall MSHR hits
|
|
system.l2c.ReadReq_mshr_misses::cpu0.inst 285 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu0.data 66 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.inst 7 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.data 1 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu2.inst 9 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu2.data 2 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu3.inst 53 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu3.data 7 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 18 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu2.data 20 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu3.data 19 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 85 # number of UpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 14 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu2.data 14 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu3.data 15 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 142 # number of ReadExReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.inst 285 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.data 165 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 7 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 15 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.inst 9 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.data 16 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu3.inst 53 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu3.data 22 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 572 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.inst 285 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.data 165 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 7 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 15 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.inst 9 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.data 16 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu3.inst 53 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu3.data 22 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 11406500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 2640000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 282500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 40000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 360000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 80000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 2120000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu3.data 280000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::total 17209000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1124491 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 722495 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 800000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 761996 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 3408982 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3960000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 565000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 566500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 609500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 5701000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.inst 11406500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.data 6600000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 282500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 605000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.inst 360000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.data 646500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu3.inst 2120000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu3.data 889500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 22910000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 11406500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.data 6600000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 282500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 605000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.inst 360000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.data 646500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu3.inst 2120000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu3.data 889500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 22910000 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.090909 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.024523 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.181818 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.144809 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.636364 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.257485 # mshr miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.977011 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.024523 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.data 0.640000 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.144809 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu3.data 0.846154 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.024523 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.data 0.640000 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.144809 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu3.data 0.846154 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40022.807018 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40357.142857 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.930233 # average ReadReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40160.392857 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40138.611111 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40105.052632 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40105.670588 # average UpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40357.142857 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40464.285714 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40633.333333 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40147.887324 # average ReadExReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40022.807018 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40357.142857 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40333.333333 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40406.250000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40431.818182 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 40052.447552 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40022.807018 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40357.142857 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40333.333333 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40406.250000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40431.818182 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 40052.447552 # average overall mshr miss latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|