c4029ecb30
the nsgige state machine can run. The frequency is of the actual state transitions, and not the rate of what underlying instructions might run at. dev/ns_gige.cc: Implement a state machine clock that acutally limits how fast the state machine can run. After each state transition, a variable is kept to hold the next state transition until the next clock. The frequency is of the actual state transitions, and not the rate of what underlying instructions might run at. dev/ns_gige.hh: Add back the rxKickEvent and txKickEvent events. python/m5/objects/Ethernet.py: Default the state machine clock to '0ns' so the default behaviour doesn't change when we actually implement the state machine clock. --HG-- extra : convert_revision : 2db1943dee4e91ea75aaee6a91e88f27f01a09dd |
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.. | ||
AlphaConsole.py | ||
AlphaFullCPU.py | ||
AlphaTLB.py | ||
BadDevice.py | ||
BaseCache.py | ||
BaseCPU.py | ||
Bus.py | ||
CoherenceProtocol.py | ||
Device.py | ||
DiskImage.py | ||
Ethernet.py | ||
Ide.py | ||
IntrControl.py | ||
MemTest.py | ||
Pci.py | ||
PhysicalMemory.py | ||
Platform.py | ||
Process.py | ||
Repl.py | ||
Root.py | ||
SimConsole.py | ||
SimpleDisk.py | ||
System.py | ||
Tsunami.py | ||
Uart.py |