Andreas Hansson b93c912013 mem: Remove redundant is_top_level cache parameter ... This patch takes the final step in removing the is_top_level parameter from the cache. With the recent changes to read requests and write invalidations, the parameter is no longer needed, and consequently removed. This also means that asymmetric cache hierarchies are now fully supported (and we are actually using them already with L1 caches, but no table-walker caches, connected to a shared L2).		2015-07-03 10:14:43 -04:00
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Benchmarks.py	config: Specify OS type and release on command line	2015-03-19 04:06:14 -04:00
CacheConfig.py	mem: Allow read-only caches and check compliance	2015-07-03 10:14:39 -04:00
Caches.py	mem: Remove redundant is_top_level cache parameter	2015-07-03 10:14:43 -04:00
cpu2000.py	arm: Add support for ARMv8 (AArch64 & AArch32)	2014-01-24 15:29:34 -06:00
CpuConfig.py	kvm, arm: Add support for aarch64	2015-06-01 19:44:19 +01:00
FSConfig.py	config: Support full-system with SST's memory system	2015-04-08 15:56:06 -05:00
MemConfig.py	config: Remove memory aliases and rely on class name	2015-04-20 12:46:29 -04:00
O3_ARM_v7a.py	mem: Remove redundant is_top_level cache parameter	2015-07-03 10:14:43 -04:00
Options.py	config: enable setting SE-mode environment variables from file	2015-04-23 13:40:18 -07:00
Simulation.py	config, cpu: fix progress interval for switched CPUs	2015-04-14 11:01:10 -05:00
SysPaths.py	config: expand '~' and '~user' in paths	2015-03-23 16:14:19 -07:00