80d9be86e6
Even though we're not incorrect about operator precedence, let's add some parens in some particularly confusing places to placate GCC 4.3 so that we don't have to turn the warning off. Agreed that this is a bit of a pain for those users who get the order of operations correct, but it is likely to prevent bugs in certain cases.
265 lines
6.6 KiB
C++
265 lines
6.6 KiB
C++
/*
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*/
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#include "arch/mips/isa_traits.hh"
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#include "arch/mips/utility.hh"
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#include "config/full_system.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/static_inst.hh"
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#include "sim/serialize.hh"
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#include "base/bitfield.hh"
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#include "base/misc.hh"
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#if FULL_SYSTEM
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#include "arch/mips/vtophys.hh"
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#include "mem/vport.hh"
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#endif
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using namespace MipsISA;
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using namespace std;
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namespace MipsISA {
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uint64_t
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getArgument(ThreadContext *tc, int number, bool fp)
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{
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#if FULL_SYSTEM
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if (number < NumArgumentRegs) {
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if (fp)
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return tc->readFloatRegBits(ArgumentReg[number]);
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else
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return tc->readIntReg(ArgumentReg[number]);
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} else {
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Addr sp = tc->readIntReg(StackPointerReg);
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VirtualPort *vp = tc->getVirtPort();
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uint64_t arg = vp->read<uint64_t>(sp +
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(number-NumArgumentRegs) * sizeof(uint64_t));
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return arg;
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}
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#else
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panic("getArgument() is Full system only\n");
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M5_DUMMY_RETURN
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#endif
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}
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uint64_t
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fpConvert(ConvertType cvt_type, double fp_val)
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{
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switch (cvt_type)
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{
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case SINGLE_TO_DOUBLE:
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{
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double sdouble_val = fp_val;
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void *sdouble_ptr = &sdouble_val;
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uint64_t sdp_bits = *(uint64_t *) sdouble_ptr;
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return sdp_bits;
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}
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case SINGLE_TO_WORD:
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{
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int32_t sword_val = (int32_t) fp_val;
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void *sword_ptr = &sword_val;
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uint64_t sword_bits= *(uint32_t *) sword_ptr;
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return sword_bits;
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}
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case WORD_TO_SINGLE:
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{
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float wfloat_val = fp_val;
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void *wfloat_ptr = &wfloat_val;
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uint64_t wfloat_bits = *(uint32_t *) wfloat_ptr;
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return wfloat_bits;
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}
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case WORD_TO_DOUBLE:
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{
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double wdouble_val = fp_val;
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void *wdouble_ptr = &wdouble_val;
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uint64_t wdp_bits = *(uint64_t *) wdouble_ptr;
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return wdp_bits;
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}
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default:
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panic("Invalid Floating Point Conversion Type (%d). See \"types.hh\" for List of Conversions\n",cvt_type);
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return 0;
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}
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}
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double
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roundFP(double val, int digits)
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{
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double digit_offset = pow(10.0,digits);
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val = val * digit_offset;
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val = val + 0.5;
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val = floor(val);
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val = val / digit_offset;
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return val;
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}
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double
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truncFP(double val)
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{
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int trunc_val = (int) val;
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return (double) trunc_val;
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}
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bool
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getCondCode(uint32_t fcsr, int cc_idx)
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{
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int shift = (cc_idx == 0) ? 23 : cc_idx + 24;
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bool cc_val = (fcsr >> shift) & 0x00000001;
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return cc_val;
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}
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uint32_t
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genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val)
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{
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int cc_idx = (cc_num == 0) ? 23 : cc_num + 24;
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fcsr = bits(fcsr, 31, cc_idx + 1) << (cc_idx + 1) |
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cc_val << cc_idx |
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bits(fcsr, cc_idx - 1, 0);
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return fcsr;
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}
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uint32_t
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genInvalidVector(uint32_t fcsr_bits)
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{
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//Set FCSR invalid in "flag" field
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int invalid_offset = Invalid + Flag_Field;
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fcsr_bits = fcsr_bits | (1 << invalid_offset);
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//Set FCSR invalid in "cause" flag
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int cause_offset = Invalid + Cause_Field;
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fcsr_bits = fcsr_bits | (1 << cause_offset);
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return fcsr_bits;
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}
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bool
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isNan(void *val_ptr, int size)
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{
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switch (size)
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{
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case 32:
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{
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uint32_t val_bits = *(uint32_t *) val_ptr;
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return (bits(val_bits, 30, 23) == 0xFF);
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}
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case 64:
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{
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uint64_t val_bits = *(uint64_t *) val_ptr;
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return (bits(val_bits, 62, 52) == 0x7FF);
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}
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default:
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panic("Type unsupported. Size mismatch\n");
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}
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}
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bool
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isQnan(void *val_ptr, int size)
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{
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switch (size)
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{
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case 32:
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{
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uint32_t val_bits = *(uint32_t *) val_ptr;
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return (bits(val_bits, 30, 22) == 0x1FE);
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}
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case 64:
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{
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uint64_t val_bits = *(uint64_t *) val_ptr;
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return (bits(val_bits, 62, 51) == 0xFFE);
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}
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default:
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panic("Type unsupported. Size mismatch\n");
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}
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}
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bool
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isSnan(void *val_ptr, int size)
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{
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switch (size)
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{
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case 32:
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{
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uint32_t val_bits = *(uint32_t *) val_ptr;
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return (bits(val_bits, 30, 22) == 0x1FF);
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}
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case 64:
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{
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uint64_t val_bits = *(uint64_t *) val_ptr;
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return (bits(val_bits, 62, 51) == 0xFFF);
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}
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default:
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panic("Type unsupported. Size mismatch\n");
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}
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}
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void
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copyRegs(ThreadContext *src, ThreadContext *dest)
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{
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panic("Copy Regs Not Implemented Yet\n");
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}
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void
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copyMiscRegs(ThreadContext *src, ThreadContext *dest)
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{
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panic("Copy Misc. Regs Not Implemented Yet\n");
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}
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template <class CPU>
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void
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zeroRegisters(CPU *cpu)
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{
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// Insure ISA semantics
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// (no longer very clean due to the change in setIntReg() in the
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// cpu model. Consider changing later.)
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cpu->thread->setIntReg(ZeroReg, 0);
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cpu->thread->setFloatReg(ZeroReg, 0.0);
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}
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void
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startupCPU(ThreadContext *tc, int cpuId)
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{
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tc->activate(0/*tc->getThreadNum()*/);
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}
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} // namespace MipsISA
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