192 lines
6.3 KiB
C++
Executable file
192 lines
6.3 KiB
C++
Executable file
/*
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Rick Strong
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*/
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#ifndef __ARCH_MIPS_INTERRUPT_HH__
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#define __ARCH_MIPS_INTERRUPT_HH__
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#include "arch/mips/faults.hh"
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#include "base/compiler.hh"
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namespace MipsISA
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{
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class Interrupts
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{
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/*
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protected:
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uint8_t intstatus;
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bool oncputimerintr;
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public:
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Interrupts()
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{
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intstatus = 0;
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newInfoSet = false;
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oncputimerintr = false;
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}
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// post(int int_num, int index) is responsible
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// for posting an interrupt. It sets a bit
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// in intstatus corresponding to Cause IP*. The
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// MIPS register Cause is updated by updateIntrInfo
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// which is called by check_interrupts
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//
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void post(int int_num, int index);
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// clear(int int_num, int index) is responsible
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// for clearing an interrupt. It clear a bit
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// in intstatus corresponding to Cause IP*. The
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// MIPS register Cause is updated by updateIntrInfo
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// which is called by check_interrupts
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//
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void clear(int int_num, int index);
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// clear_all() is responsible
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// for clearing all interrupts. It clears all bits
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// in intstatus corresponding to Cause IP*. The
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// MIPS register Cause is updated by updateIntrInfo
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// which is called by check_interrupts
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//
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void clear_all();
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// getInterrupt(ThreadContext * tc) checks if an interrupt
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// should be returned. It ands the interrupt mask and
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// and interrupt pending bits to see if one exists. It
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// also makes sure interrupts are enabled (IE) and
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// that ERL and ERX are not set
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//
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Fault getInterrupt(ThreadContext * tc);
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// updateIntrInfo(ThreadContext *tc) const syncs the
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// MIPS cause register with the instatus variable. instatus
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// is essentially a copy of the MIPS cause[IP7:IP0]
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//
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void updateIntrInfo(ThreadContext *tc) const;
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void updateIntrInfoCpuTimerIntr(ThreadContext *tc) const;
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bool onCpuTimerInterrupt(ThreadContext *tc) const;
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bool check_interrupts(ThreadContext * tc) const{
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//return (intstatus != 0) && !(tc->readPC() & 0x3);
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if (oncputimerintr == false){
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updateIntrInfo(tc);
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return ((intstatus != 0) || onCpuTimerInterrupt(tc));
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}
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else
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return true;
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}
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*/
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protected:
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//uint8_t intstatus;
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//bool oncputimerintr;
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public:
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Interrupts()
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{
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//intstatus = 0;
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newInfoSet = false;
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//oncputimerintr = false;
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}
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// post(int int_num, int index) is responsible
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// for posting an interrupt. It sets a bit
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// in intstatus corresponding to Cause IP*. The
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// MIPS register Cause is updated by updateIntrInfo
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// which is called by check_interrupts
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//
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void post(int int_num, ThreadContext* tc);
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void post(int int_num, int index);
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// clear(int int_num, int index) is responsible
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// for clearing an interrupt. It clear a bit
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// in intstatus corresponding to Cause IP*. The
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// MIPS register Cause is updated by updateIntrInfo
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// which is called by check_interrupts
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//
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void clear(int int_num, ThreadContext* tc);
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void clear(int int_num, int index);
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// clear_all() is responsible
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// for clearing all interrupts. It clears all bits
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// in intstatus corresponding to Cause IP*. The
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// MIPS register Cause is updated by updateIntrInfo
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// which is called by check_interrupts
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//
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void clear_all(ThreadContext* tc);
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void clear_all();
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// getInterrupt(ThreadContext * tc) checks if an interrupt
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// should be returned. It ands the interrupt mask and
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// and interrupt pending bits to see if one exists. It
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// also makes sure interrupts are enabled (IE) and
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// that ERL and ERX are not set
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//
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Fault getInterrupt(ThreadContext * tc);
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// updateIntrInfo(ThreadContext *tc) const syncs the
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// MIPS cause register with the instatus variable. instatus
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// is essentially a copy of the MIPS cause[IP7:IP0]
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//
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void updateIntrInfo(ThreadContext *tc) const;
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bool interruptsPending(ThreadContext *tc) const;
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bool onCpuTimerInterrupt(ThreadContext *tc) const;
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bool check_interrupts(ThreadContext * tc) const{
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return interruptsPending(tc);
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}
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void serialize(std::ostream &os)
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{
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fatal("Serialization of Interrupts Unimplemented for MIPS");
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//SERIALIZE_ARRAY(interrupts, NumInterruptLevels);
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//SERIALIZE_SCALAR(intstatus);
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}
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void unserialize(Checkpoint *cp, const std::string §ion)
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{
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fatal("Unserialization of Interrupts Unimplemented for MIPS");
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//UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels);
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//UNSERIALIZE_SCALAR(intstatus);
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}
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private:
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bool newInfoSet;
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int newIpl;
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int newSummary;
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};
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}
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#endif
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