c3268f8820
This patch adds an example configuration in ext/sst/tests/ that allows an SST/gem5 instance to simulate a 4-core AArch64 system with SST's memHierarchy components providing all the caches and memories. |
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.. | ||
Benchmarks.py | ||
CacheConfig.py | ||
Caches.py | ||
cpu2000.py | ||
CpuConfig.py | ||
FSConfig.py | ||
MemConfig.py | ||
O3_ARM_v7a.py | ||
Options.py | ||
Simulation.py | ||
SysPaths.py |