gem5/src/mem
Nathan Binkert c25d966b06 Clean up the SimpleTimingPort class a little bit.
Move the constructor into the .cc file and get rid of the typedef for
SendEvent.
2008-11-10 11:51:18 -08:00
..
cache Cache: Refactor packet forwarding a bit. 2008-11-10 14:10:28 -08:00
config remove the totally obsolete split cache 2008-10-23 16:11:28 -04:00
bridge.cc eventq: convert all usage of events to use the new API. 2008-10-09 04:58:24 -07:00
bridge.hh eventq: convert all usage of events to use the new API. 2008-10-09 04:58:24 -07:00
Bridge.py DMA: Add IOCache and fix bus bridge to optionally only send requests one 2007-08-10 16:14:01 -04:00
bus.cc eventq: convert all usage of events to use the new API. 2008-10-09 04:58:24 -07:00
bus.hh Backed out changeset 94a7bb476fca: caused memory leak. 2008-06-28 13:19:38 -04:00
Bus.py Bus: Fix the bus timing to be more realistic. 2008-02-26 02:20:08 -05:00
dram.cc style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs 2008-09-10 14:26:15 -04:00
dram.hh Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
mem_object.cc params: Get rid of the remnants of the old style parameter configuration stuff. 2008-08-11 12:22:17 -07:00
mem_object.hh params: Get rid of the remnants of the old style parameter configuration stuff. 2008-08-11 12:22:17 -07:00
MemObject.py Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
mport.cc Create a message port for sending messages as apposed to reading/writing a memory range. 2008-10-12 12:08:51 -07:00
mport.hh Create a message port for sending messages as apposed to reading/writing a memory range. 2008-10-12 12:08:51 -07:00
packet.cc style: clean up the Packet stuff 2008-11-10 11:51:17 -08:00
packet.hh style: clean up the Packet stuff 2008-11-10 11:51:17 -08:00
packet_access.hh style: clean up the Packet stuff 2008-11-10 11:51:17 -08:00
page_table.cc Checkpointing: Name SE page table entries better so that there isn't a problem if multiple workloads are being run at once. 2007-11-14 23:42:08 -05:00
page_table.hh TLB: Fix serialization issues with the tlb entries and make the page table store the process, not the system. 2007-10-25 19:04:44 -07:00
physical.cc Add in Context IDs to the simulator. From now on, cpuId is almost never used, 2008-11-02 21:57:07 -05:00
physical.hh Add in Context IDs to the simulator. From now on, cpuId is almost never used, 2008-11-02 21:57:07 -05:00
PhysicalMemory.py Make default PhysicalMemory latency slightly more realistic. 2008-08-03 18:13:29 -04:00
port.cc eventq: Major API change for the Event and EventQueue structures. 2008-10-09 04:58:23 -07:00
port.hh eventq: Major API change for the Event and EventQueue structures. 2008-10-09 04:58:23 -07:00
port_impl.hh Put the ProcessInfo and StackTrace objects into the ISA namespaces. 2006-11-08 00:52:04 -05:00
request.hh style: clean up the Packet stuff 2008-11-10 11:51:17 -08:00
SConscript Create a message port for sending messages as apposed to reading/writing a memory range. 2008-10-12 12:08:51 -07:00
tport.cc Clean up the SimpleTimingPort class a little bit. 2008-11-10 11:51:18 -08:00
tport.hh Clean up the SimpleTimingPort class a little bit. 2008-11-10 11:51:18 -08:00
translating_port.cc fix the translating ports so it can add a page on a fault 2007-05-09 15:37:46 -04:00
translating_port.hh fix the translating ports so it can add a page on a fault 2007-05-09 15:37:46 -04:00
vport.cc Remove delVirtPort() and make getVirtPort() only return cached version. 2008-07-01 10:25:07 -04:00
vport.hh implement vtophys and 32bit gdb support 2007-02-18 19:57:46 -05:00