13a15c55a4
Coherence protocol change basically got rid of UpgradeReqs in L2 caches, other minor related cache stat changes.
217 lines
24 KiB
Text
217 lines
24 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 1333935 # Simulator instruction rate (inst/s)
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host_mem_usage 197236 # Number of bytes of host memory used
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host_seconds 1116.64 # Real time elapsed on the host
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host_tick_rate 1848636408 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 1489523295 # Number of instructions simulated
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sim_seconds 2.064259 # Number of seconds simulated
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sim_ticks 2064258667000 # Number of ticks simulated
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system.cpu.dcache.ReadReq_accesses 402512844 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 20775.839079 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17775.839079 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 402319358 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 4019834000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 193486 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 3439376000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 193486 # number of ReadReq MSHR misses
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system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
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system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency
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system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency
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system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits
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system.cpu.dcache.SwapReq_miss_latency 392000 # number of SwapReq miss cycles
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system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses
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system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses
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system.cpu.dcache.SwapReq_mshr_miss_latency 371000 # number of SwapReq MSHR miss cycles
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system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses
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system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 23705.368693 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20705.368693 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 166587088 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 6156948000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.001557 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 259728 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 5377764000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.001557 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 259728 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 569359660 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 22454.694692 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 19454.694692 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 568906446 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 10176782000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.000796 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 453214 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 8817140000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.000796 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 453214 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.occ_%::0 0.999811 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 4095.226955 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 22454.694692 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 19454.694692 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 568906446 # number of overall hits
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system.cpu.dcache.overall_miss_latency 10176782000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.000796 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 453214 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 8817140000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.000796 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 453214 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 449125 # number of replacements
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system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4095.226955 # Cycle average of tags in use
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system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 566994000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 407009 # number of writebacks
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system.cpu.icache.ReadReq_accesses 1485113012 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 55848.238482 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 1485111905 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 61824000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 1107 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 58503000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 1107 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 1341564.503162 # Average number of references to valid blocks.
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 1485113012 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 55848.238482 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency
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system.cpu.icache.demand_hits 1485111905 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 61824000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
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system.cpu.icache.demand_misses 1107 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 58503000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 1107 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.occ_%::0 0.442603 # Average percentage of cache occupancy
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system.cpu.icache.occ_blocks::0 906.450625 # Average occupied blocks per context
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system.cpu.icache.overall_accesses 1485113012 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 1485111905 # number of overall hits
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system.cpu.icache.overall_miss_latency 61824000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
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system.cpu.icache.overall_misses 1107 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 58503000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 1107 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 118 # number of replacements
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system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 906.450625 # Cycle average of tags in use
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system.cpu.icache.total_refs 1485111905 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.l2cache.ReadExReq_accesses 259735 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadExReq_hits 199710 # number of ReadExReq hits
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system.cpu.l2cache.ReadExReq_miss_latency 3121300000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_rate 0.231101 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_misses 60025 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 2401000000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.231101 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_mshr_misses 60025 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadReq_accesses 194593 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_hits 162275 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_miss_latency 1680536000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_rate 0.166080 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_misses 32318 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency 1292720000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate 0.166080 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_misses 32318 # number of ReadReq MSHR misses
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system.cpu.l2cache.Writeback_accesses 407009 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.Writeback_hits 407009 # number of Writeback hits
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_refs 4.765989 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.demand_accesses 454328 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.demand_hits 361985 # number of demand (read+write) hits
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system.cpu.l2cache.demand_miss_latency 4801836000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_rate 0.203252 # miss rate for demand accesses
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system.cpu.l2cache.demand_misses 92343 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.demand_mshr_miss_latency 3693720000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_rate 0.203252 # mshr miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_misses 92343 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.occ_%::0 0.057187 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_%::1 0.483685 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_blocks::0 1873.919591 # Average occupied blocks per context
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system.cpu.l2cache.occ_blocks::1 15849.385934 # Average occupied blocks per context
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system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_hits 361985 # number of overall hits
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system.cpu.l2cache.overall_miss_latency 4801836000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_rate 0.203252 # miss rate for overall accesses
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system.cpu.l2cache.overall_misses 92343 # number of overall misses
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.l2cache.overall_mshr_miss_latency 3693720000 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_rate 0.203252 # mshr miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_misses 92343 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.l2cache.replacements 74112 # number of replacements
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system.cpu.l2cache.sampled_refs 89611 # Sample count of references to valid blocks.
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.l2cache.tagsinuse 17723.305524 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 427085 # Total number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.writebacks 59035 # number of writebacks
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 4128517334 # number of cpu cycles simulated
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system.cpu.num_insts 1489523295 # Number of instructions executed
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system.cpu.num_refs 569365767 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 49 # Number of system calls
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---------- End Simulation Statistics ----------
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