5a15909bac
This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
1827 lines
215 KiB
Text
1827 lines
215 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 1.194911 # Number of seconds simulated
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sim_ticks 1194911360500 # Number of ticks simulated
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final_tick 1194911360500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 773513 # Simulator instruction rate (inst/s)
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host_op_rate 985724 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 15060857671 # Simulator tick rate (ticks/s)
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host_mem_usage 403580 # Number of bytes of host memory used
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host_seconds 79.34 # Real time elapsed on the host
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sim_insts 61369589 # Number of instructions simulated
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sim_ops 78206230 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 464036 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 6626228 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 256092 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 2904304 # Number of bytes read from this memory
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system.physmem.bytes_read::total 62155620 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 464036 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 256092 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 720128 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 4136576 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 3027304 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7163920 # Number of bytes written to this memory
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system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 13469 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 103607 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 4083 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 45406 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 6654636 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 64634 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 756826 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 821470 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.clcd 43437960 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.dtb.walker 214 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 388343 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 5545372 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 214319 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 2430560 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 52016930 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 388343 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 214319 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 602662 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 3461827 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 2533497 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 33 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 5995357 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 3461827 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.clcd 43437960 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 388343 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 8078869 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 214319 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 2430594 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 58012286 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 6654636 # Total number of read requests seen
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system.physmem.writeReqs 821470 # Total number of write requests seen
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system.physmem.cpureqs 235013 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 425896704 # Total number of bytes read from memory
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system.physmem.bytesWritten 52574080 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 62155620 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 7163920 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 138 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 10632 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 415730 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 415559 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 414961 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 415336 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 422399 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 415419 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 415520 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 415301 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 415351 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 415631 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 415270 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 414902 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 415547 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 416081 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 415762 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 415729 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 50036 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 49924 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 51325 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 51581 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 51864 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 51435 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 51646 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 51467 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 51327 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 51592 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 51318 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 51082 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 51567 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 51872 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 51738 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 51696 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 1194906959500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 6825 # Categorize read packet sizes
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system.physmem.readPktSize::3 6488064 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 159747 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 756836 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 64634 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 581277 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 421174 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 435266 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 1590102 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 1186915 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1183214 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1164468 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 13127 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 10448 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 15751 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 21053 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 15489 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 4169 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 4068 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 3980 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 3919 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 77 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 35694 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 35715 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 35716 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 35716 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 35716 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 35716 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 35716 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 35716 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 35716 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 35716 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 35716 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 35716 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 35716 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 35716 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 35716 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 35716 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 35716 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 35716 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 35716 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 35716 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 35716 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 35716 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 35716 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 23 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 34668 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 13801.223030 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 734.240341 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 27780.651463 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::64-127 7945 22.92% 22.92% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-191 4005 11.55% 34.47% # Bytes accessed per row activation
|
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system.physmem.bytesPerActivate::192-255 2676 7.72% 42.19% # Bytes accessed per row activation
|
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system.physmem.bytesPerActivate::256-319 1963 5.66% 47.85% # Bytes accessed per row activation
|
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system.physmem.bytesPerActivate::320-383 1415 4.08% 51.93% # Bytes accessed per row activation
|
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system.physmem.bytesPerActivate::384-447 1138 3.28% 55.22% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::448-511 895 2.58% 57.80% # Bytes accessed per row activation
|
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system.physmem.bytesPerActivate::512-575 859 2.48% 60.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::576-639 666 1.92% 62.20% # Bytes accessed per row activation
|
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system.physmem.bytesPerActivate::640-703 565 1.63% 63.83% # Bytes accessed per row activation
|
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system.physmem.bytesPerActivate::704-767 463 1.34% 65.16% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-831 439 1.27% 66.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::832-895 280 0.81% 67.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-959 254 0.73% 67.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::960-1023 189 0.55% 68.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1087 312 0.90% 69.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1088-1151 134 0.39% 69.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1152-1215 136 0.39% 70.19% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1216-1279 130 0.37% 70.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1280-1343 99 0.29% 70.85% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1344-1407 89 0.26% 71.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1408-1471 164 0.47% 71.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1472-1535 949 2.74% 74.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1536-1599 269 0.78% 75.10% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1600-1663 135 0.39% 75.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1664-1727 116 0.33% 75.82% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1728-1791 100 0.29% 76.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1792-1855 85 0.25% 76.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1856-1919 65 0.19% 76.54% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1920-1983 50 0.14% 76.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1984-2047 50 0.14% 76.83% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2048-2111 59 0.17% 77.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2112-2175 33 0.10% 77.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2176-2239 32 0.09% 77.19% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2240-2303 20 0.06% 77.24% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2304-2367 23 0.07% 77.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2368-2431 11 0.03% 77.34% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2432-2495 23 0.07% 77.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2496-2559 27 0.08% 77.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2560-2623 12 0.03% 77.52% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2624-2687 11 0.03% 77.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2688-2751 15 0.04% 77.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2752-2815 7 0.02% 77.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2816-2879 13 0.04% 77.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2880-2943 8 0.02% 77.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2944-3007 13 0.04% 77.71% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3008-3071 9 0.03% 77.74% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3072-3135 14 0.04% 77.78% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3136-3199 9 0.03% 77.81% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3200-3263 16 0.05% 77.85% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3264-3327 6 0.02% 77.87% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3328-3391 9 0.03% 77.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3392-3455 7 0.02% 77.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3456-3519 9 0.03% 77.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3520-3583 6 0.02% 77.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3584-3647 6 0.02% 77.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3648-3711 8 0.02% 78.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3712-3775 9 0.03% 78.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3776-3839 8 0.02% 78.05% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3840-3903 6 0.02% 78.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3904-3967 7 0.02% 78.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3968-4031 9 0.03% 78.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4032-4095 6 0.02% 78.13% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4096-4159 45 0.13% 78.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4160-4223 4 0.01% 78.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4224-4287 6 0.02% 78.29% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4288-4351 9 0.03% 78.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4352-4415 2 0.01% 78.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4416-4479 4 0.01% 78.33% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4480-4543 6 0.02% 78.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4544-4607 8 0.02% 78.37% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4608-4671 6 0.02% 78.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4672-4735 4 0.01% 78.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4736-4799 3 0.01% 78.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4800-4863 3 0.01% 78.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4864-4927 5 0.01% 78.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4928-4991 2 0.01% 78.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4992-5055 8 0.02% 78.46% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5056-5119 2 0.01% 78.47% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5120-5183 3 0.01% 78.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5184-5247 1 0.00% 78.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5376-5439 2 0.01% 78.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5440-5503 1 0.00% 78.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5504-5567 1 0.00% 78.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5568-5631 5 0.01% 78.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5632-5695 6 0.02% 78.52% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5696-5759 2 0.01% 78.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5760-5823 1 0.00% 78.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5824-5887 1 0.00% 78.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5888-5951 6 0.02% 78.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6016-6079 6 0.02% 78.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6144-6207 180 0.52% 79.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6208-6271 1 0.00% 79.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6272-6335 4 0.01% 79.10% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6336-6399 1 0.00% 79.10% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6400-6463 5 0.01% 79.12% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6464-6527 1 0.00% 79.12% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6528-6591 1 0.00% 79.12% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6592-6655 1 0.00% 79.13% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6656-6719 3 0.01% 79.14% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6720-6783 2 0.01% 79.14% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6784-6847 21 0.06% 79.20% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6848-6911 2 0.01% 79.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6912-6975 1 0.00% 79.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6976-7039 1 0.00% 79.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7040-7103 2 0.01% 79.22% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7104-7167 2 0.01% 79.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7168-7231 6 0.02% 79.24% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7296-7359 1 0.00% 79.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7360-7423 1 0.00% 79.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7488-7551 3 0.01% 79.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7552-7615 3 0.01% 79.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7616-7679 3 0.01% 79.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7680-7743 3 0.01% 79.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7744-7807 1 0.00% 79.29% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7808-7871 3 0.01% 79.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7872-7935 6 0.02% 79.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7936-7999 6 0.02% 79.33% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8000-8063 3 0.01% 79.34% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8064-8127 7 0.02% 79.36% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8128-8191 5 0.01% 79.37% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8192-8255 319 0.92% 80.29% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8448-8511 2 0.01% 80.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8704-8767 1 0.00% 80.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8960-9023 1 0.00% 80.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9216-9279 2 0.01% 80.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9408-9471 1 0.00% 80.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9472-9535 1 0.00% 80.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9600-9663 1 0.00% 80.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9984-10047 2 0.01% 80.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10240-10303 18 0.05% 80.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10496-10559 2 0.01% 80.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11264-11327 2 0.01% 80.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11520-11583 1 0.00% 80.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11776-11839 1 0.00% 80.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12032-12095 1 0.00% 80.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12544-12607 1 0.00% 80.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12800-12863 2 0.01% 80.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12928-12991 1 0.00% 80.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13056-13119 1 0.00% 80.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13312-13375 3 0.01% 80.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13824-13887 1 0.00% 80.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14080-14143 1 0.00% 80.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14336-14399 1 0.00% 80.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14784-14847 1 0.00% 80.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15104-15167 2 0.01% 80.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15360-15423 3 0.01% 80.45% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15616-15679 1 0.00% 80.45% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16384-16447 1 0.00% 80.45% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16640-16703 2 0.01% 80.46% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16832-16895 1 0.00% 80.46% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16896-16959 2 0.01% 80.47% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17152-17215 2 0.01% 80.47% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17664-17727 1 0.00% 80.47% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18176-18239 2 0.01% 80.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18432-18495 1 0.00% 80.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18752-18815 1 0.00% 80.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19328-19391 1 0.00% 80.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19456-19519 4 0.01% 80.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19712-19775 1 0.00% 80.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20224-20287 1 0.00% 80.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20480-20543 13 0.04% 80.54% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20736-20799 1 0.00% 80.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20992-21055 2 0.01% 80.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21504-21567 2 0.01% 80.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21760-21823 1 0.00% 80.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22016-22079 2 0.01% 80.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22272-22335 2 0.01% 80.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22528-22591 1 0.00% 80.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22784-22847 1 0.00% 80.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23552-23615 4 0.01% 80.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24320-24383 2 0.01% 80.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24576-24639 4 0.01% 80.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25344-25407 1 0.00% 80.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25600-25663 3 0.01% 80.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25856-25919 1 0.00% 80.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26112-26175 2 0.01% 80.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26368-26431 3 0.01% 80.64% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26624-26687 2 0.01% 80.64% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::27392-27455 2 0.01% 80.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::27648-27711 1 0.00% 80.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28416-28479 1 0.00% 80.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28672-28735 1 0.00% 80.66% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29312-29375 1 0.00% 80.66% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29504-29567 1 0.00% 80.66% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29696-29759 3 0.01% 80.67% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29952-30015 1 0.00% 80.67% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30208-30271 2 0.01% 80.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30400-30463 1 0.00% 80.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30464-30527 3 0.01% 80.69% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30720-30783 6 0.02% 80.71% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31232-31295 2 0.01% 80.71% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31488-31551 3 0.01% 80.72% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31744-31807 2 0.01% 80.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31872-31935 1 0.00% 80.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::32256-32319 1 0.00% 80.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::32512-32575 1 0.00% 80.74% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33024-33087 16 0.05% 80.78% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33088-33151 1 0.00% 80.79% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33152-33215 2 0.01% 80.79% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33280-33343 36 0.10% 80.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::34304-34367 1 0.00% 80.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35584-35647 1 0.00% 80.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35840-35903 1 0.00% 80.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::38144-38207 1 0.00% 80.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::38400-38463 1 0.00% 80.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::39488-39551 1 0.00% 80.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41216-41279 1 0.00% 80.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41344-41407 1 0.00% 80.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41984-42047 1 0.00% 80.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43008-43071 1 0.00% 80.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43584-43647 1 0.00% 80.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44032-44095 1 0.00% 80.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44544-44607 1 0.00% 80.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::45056-45119 1 0.00% 80.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::45824-45887 1 0.00% 80.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::48640-48703 2 0.01% 80.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::49152-49215 1 0.00% 80.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::50176-50239 1 0.00% 80.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::50432-50495 2 0.01% 80.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::51520-51583 1 0.00% 80.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::52224-52287 4 0.01% 80.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::52800-52863 1 0.00% 80.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::54272-54335 2 0.01% 80.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::55296-55359 1 0.00% 80.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::56064-56127 1 0.00% 80.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::56320-56383 2 0.01% 80.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::61440-61503 2 0.01% 81.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::61696-61759 1 0.00% 81.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::62080-62143 1 0.00% 81.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::62208-62271 1 0.00% 81.01% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::62464-62527 1 0.00% 81.01% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::62976-63039 1 0.00% 81.01% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::63488-63551 2 0.01% 81.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::64512-64575 2 0.01% 81.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::64832-64895 1 0.00% 81.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::65024-65087 6 0.02% 81.04% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::65152-65215 2 0.01% 81.05% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::65216-65279 1 0.00% 81.05% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::65344-65407 1 0.00% 81.05% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::65472-65535 6 0.02% 81.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::65536-65599 6196 17.87% 98.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::72768-72831 1 0.00% 98.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::73920-73983 1 0.00% 98.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::75008-75071 1 0.00% 98.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::82944-83007 1 0.00% 98.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::84480-84543 1 0.00% 98.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::85376-85439 1 0.00% 98.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::85568-85631 1 0.00% 98.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::94656-94719 1 0.00% 98.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::95552-95615 1 0.00% 98.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::98944-99007 1 0.00% 98.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::99520-99583 1 0.00% 98.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::109120-109183 1 0.00% 98.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::109696-109759 1 0.00% 98.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::110080-110143 1 0.00% 98.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::117440-117503 1 0.00% 98.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::117952-118015 1 0.00% 98.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::120256-120319 1 0.00% 98.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::120640-120703 1 0.00% 99.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::121152-121215 1 0.00% 99.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::129856-129919 1 0.00% 99.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::130112-130175 1 0.00% 99.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::131072-131135 336 0.97% 99.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::131200-131263 1 0.00% 99.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::132096-132159 3 0.01% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::136576-136639 1 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::196160-196223 1 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::196608-196671 2 0.01% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 34668 # Bytes accessed per row activation
|
|
system.physmem.totQLat 132807422500 # Total cycles spent in queuing delays
|
|
system.physmem.totMemAccLat 174630638750 # Sum of mem lat for all requests
|
|
system.physmem.totBusLat 33272490000 # Total cycles spent in databus access
|
|
system.physmem.totBankLat 8550726250 # Total cycles spent in bank access
|
|
system.physmem.avgQLat 19957.54 # Average queueing delay per request
|
|
system.physmem.avgBankLat 1284.95 # Average bank access latency per request
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
|
system.physmem.avgMemAccLat 26242.50 # Average memory access latency
|
|
system.physmem.avgRdBW 356.43 # Average achieved read bandwidth in MB/s
|
|
system.physmem.avgWrBW 44.00 # Average achieved write bandwidth in MB/s
|
|
system.physmem.avgConsumedRdBW 52.02 # Average consumed read bandwidth in MB/s
|
|
system.physmem.avgConsumedWrBW 6.00 # Average consumed write bandwidth in MB/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
|
system.physmem.busUtil 3.13 # Data bus utilization in percentage
|
|
system.physmem.avgRdQLen 0.15 # Average read queue length over time
|
|
system.physmem.avgWrQLen 11.97 # Average write queue length over time
|
|
system.physmem.readRowHits 6636574 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 804724 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 97.96 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 159830.13 # Average gap between requests
|
|
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s)
|
|
system.membus.throughput 60028739 # Throughput (bytes/s)
|
|
system.membus.trans_dist::ReadReq 7703151 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 7703151 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 767201 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 767201 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 64634 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 27614 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 16407 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 10632 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 137758 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 137302 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382564 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1966559 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8856 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 4358923 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::system.bridge.slave 2382564 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::system.physmem.port 14942687 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::system.realview.gic.pio 8856 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 17335051 # Packet count per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389882 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17415028 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17712 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::total 19824510 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::system.bridge.slave 2389882 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::system.physmem.port 69319540 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::system.realview.gic.pio 17712 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::total 71729022 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.data_through_bus 71729022 # Total data (bytes)
|
|
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.membus.reqLayer0.occupancy 1208299500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 9149149500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.8 # Layer utilization (%)
|
|
system.membus.reqLayer3.occupancy 7960500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer5.occupancy 2500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer6.occupancy 777000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 5034294617 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 14663453747 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 1.2 # Layer utilization (%)
|
|
system.l2c.tags.replacements 69629 # number of replacements
|
|
system.l2c.tags.tagsinuse 53155.534639 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 1651678 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 134776 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 12.254986 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 40041.185718 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.667860 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001521 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 4638.655043 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 5789.348152 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001660 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 1927.060090 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 756.614595 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.610980 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.070780 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.088338 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.029405 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.011545 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.811089 # Average percentage of cache occupancy
|
|
system.l2c.ReadReq_hits::cpu0.dtb.walker 4625 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.itb.walker 1507 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.inst 482925 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.data 242050 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.dtb.walker 3554 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.itb.walker 1806 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 372304 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.data 110721 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 1219492 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 576641 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 576641 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 1408 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 418 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 1826 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu0.data 257 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu1.data 96 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 353 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 65574 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 45429 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 111003 # number of ReadExReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 4625 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 1507 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 482925 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 307624 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 3554 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 1806 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 372304 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 156150 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1330495 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 4625 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 1507 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 482925 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 307624 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 3554 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 1806 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 372304 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 156150 # number of overall hits
|
|
system.l2c.overall_hits::total 1330495 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.inst 6837 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.data 9715 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.inst 3996 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.data 1891 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 22446 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_misses::cpu0.data 3988 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 3371 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 7359 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 387 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu1.data 473 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 860 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 95120 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 44595 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 139715 # number of ReadExReq misses
|
|
system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.inst 6837 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 104835 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 3996 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 46486 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 162161 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.inst 6837 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 104835 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 3996 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 46486 # number of overall misses
|
|
system.l2c.overall_misses::total 162161 # number of overall misses
|
|
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 395750 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 122500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.inst 486019750 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.data 691389999 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.itb.walker 89250 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.inst 282135750 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.data 152148250 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::total 1612301249 # number of ReadReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu0.data 11489505 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 12402970 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 23892475 # number of UpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1837921 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1069454 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::total 2907375 # number of SCUpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 6199806193 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 2820905645 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 9020711838 # number of ReadExReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.dtb.walker 395750 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.itb.walker 122500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 486019750 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 6891196192 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.itb.walker 89250 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 282135750 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 2973053895 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 10633013087 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.dtb.walker 395750 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.itb.walker 122500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 486019750 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 6891196192 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.itb.walker 89250 # number of overall miss cycles
|
|
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|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000553 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010619 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.016792 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.018073 # mshr miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.739066 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.889681 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.801198 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.600932 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.831283 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.708986 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.591932 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.495368 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.557260 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000864 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001325 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013958 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.254171 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000553 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010619 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.229406 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.108639 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000864 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001325 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013958 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.254171 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000553 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010619 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.229406 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.108639 # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 86062.500000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58465.842598 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 58485.331858 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57979.667167 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67742.860920 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 59174.159011 # average ReadReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10008.019809 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.545535 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10016.964126 # average UpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10007.457364 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.114165 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10005.068605 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 52642.691369 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50700.972149 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 52022.922779 # average ReadExReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 86062.500000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58465.842598 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53184.125550 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57979.667167 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51394.217678 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 53012.744542 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86062.500000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58465.842598 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53184.125550 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57979.667167 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51394.217678 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 53012.744542 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
|
system.toL2Bus.throughput 118431561 # Throughput (bytes/s)
|
|
system.toL2Bus.trans_dist::ReadReq 2504925 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 2504925 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 767201 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 767201 # Transaction distribution
|
|
system.toL2Bus.trans_dist::Writeback 576641 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 27027 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 16760 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 43787 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 262499 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 262499 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 993555 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 2951402 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 5905 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 15026 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 753554 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 2880607 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma 6133 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma 11768 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count 7617950 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 31371320 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 53730420 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 6036 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 18516 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 24083596 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 27977862 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma 7228 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma 14216 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size 137209194 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.data_through_bus 137209194 # Total data (bytes)
|
|
system.toL2Bus.snoop_data_through_bus 4306024 # Total snoop data (bytes)
|
|
system.toL2Bus.reqLayer0.occupancy 4767819743 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 2217282985 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 2471819696 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 4396500 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 10398000 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer4.occupancy 1697865710 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.respLayer5.occupancy 2215426419 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.respLayer6.occupancy 4326250 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer7.occupancy 8214499 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.throughput 45438010 # Throughput (bytes/s)
|
|
system.iobus.trans_dist::ReadReq 7671400 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 7671400 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 7946 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 7946 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8062 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 2382564 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.realview_io.pio 8062 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 15358692 # Packet count per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16124 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::total 2389882 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.realview_io.pio 16124 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::total 54294394 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.data_through_bus 54294394 # Total data (bytes)
|
|
system.iobus.reqLayer0.occupancy 21350000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 4037000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 376000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 298000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%)
|
|
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 2374618000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 17765827253 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
|
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dtb.read_hits 9651794 # DTB read hits
|
|
system.cpu0.dtb.read_misses 3741 # DTB read misses
|
|
system.cpu0.dtb.write_hits 7596285 # DTB write hits
|
|
system.cpu0.dtb.write_misses 1585 # DTB write misses
|
|
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dtb.flush_entries 1811 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch
|
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dtb.read_accesses 9655535 # DTB read accesses
|
|
system.cpu0.dtb.write_accesses 7597870 # DTB write accesses
|
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dtb.hits 17248079 # DTB hits
|
|
system.cpu0.dtb.misses 5326 # DTB misses
|
|
system.cpu0.dtb.accesses 17253405 # DTB accesses
|
|
system.cpu0.itb.inst_hits 43295611 # ITB inst hits
|
|
system.cpu0.itb.inst_misses 2205 # ITB inst misses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.inst_accesses 43297816 # ITB inst accesses
|
|
system.cpu0.itb.hits 43295611 # DTB hits
|
|
system.cpu0.itb.misses 2205 # DTB misses
|
|
system.cpu0.itb.accesses 43297816 # DTB accesses
|
|
system.cpu0.numCycles 2389822721 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.committedInsts 42568710 # Number of instructions committed
|
|
system.cpu0.committedOps 53298123 # Number of ops (including micro ops) committed
|
|
system.cpu0.num_int_alu_accesses 48055390 # Number of integer alu accesses
|
|
system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses
|
|
system.cpu0.num_func_calls 1403445 # number of times a function call or return occured
|
|
system.cpu0.num_conditional_control_insts 5582451 # number of instructions that are conditional controls
|
|
system.cpu0.num_int_insts 48055390 # number of integer instructions
|
|
system.cpu0.num_fp_insts 3860 # number of float instructions
|
|
system.cpu0.num_int_register_reads 272420788 # number of times the integer registers were read
|
|
system.cpu0.num_int_register_writes 52266741 # number of times the integer registers were written
|
|
system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read
|
|
system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written
|
|
system.cpu0.num_mem_refs 18017454 # number of memory refs
|
|
system.cpu0.num_load_insts 10035613 # Number of load instructions
|
|
system.cpu0.num_store_insts 7981841 # Number of store instructions
|
|
system.cpu0.num_idle_cycles 2150296210.870201 # Number of idle cycles
|
|
system.cpu0.num_busy_cycles 239526510.129800 # Number of busy cycles
|
|
system.cpu0.not_idle_fraction 0.100228 # Percentage of non-idle cycles
|
|
system.cpu0.idle_fraction 0.899772 # Percentage of idle cycles
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 51308 # number of quiesce instructions executed
|
|
system.cpu0.icache.tags.replacements 490004 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 509.392438 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 42805077 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 490516 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 87.265404 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 76030513250 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.392438 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994907 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.994907 # Average percentage of cache occupancy
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 42805077 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 42805077 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 42805077 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 42805077 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 42805077 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 42805077 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 490517 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 490517 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 490517 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 490517 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 490517 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 490517 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6812396235 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 6812396235 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 6812396235 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 6812396235 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 6812396235 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 6812396235 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 43295594 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 43295594 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 43295594 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 43295594 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 43295594 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 43295594 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011329 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.011329 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011329 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.011329 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011329 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.011329 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13888.195995 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 13888.195995 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13888.195995 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 13888.195995 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13888.195995 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 13888.195995 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490517 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 490517 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 490517 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 490517 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 490517 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 490517 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5828002765 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 5828002765 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5828002765 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 5828002765 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5828002765 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 5828002765 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 431776750 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 431776750 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 431776750 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::total 431776750 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011329 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011329 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011329 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.011329 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011329 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.011329 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11881.347160 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11881.347160 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11881.347160 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11881.347160 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11881.347160 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11881.347160 # average overall mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.dcache.tags.replacements 406612 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 470.882465 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 15965290 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 407124 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 39.214809 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 659626250 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 470.882465 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.919692 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.919692 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 9135819 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 9135819 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 6493762 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 6493762 # number of WriteReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156506 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 156506 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 158999 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 158999 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 15629581 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 15629581 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 15629581 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 15629581 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 263761 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 263761 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 176647 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 176647 # number of WriteReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9920 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 9920 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7375 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 7375 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 440408 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 440408 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 440408 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 440408 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3882137498 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 3882137498 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7549327791 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 7549327791 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 98498000 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 98498000 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 40527887 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 40527887 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 11431465289 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 11431465289 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 11431465289 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 11431465289 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 9399580 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 9399580 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 6670409 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 6670409 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 166426 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 166426 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166374 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 166374 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 16069989 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 16069989 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 16069989 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 16069989 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028061 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.028061 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026482 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.026482 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059606 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059606 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044328 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044328 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027406 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.027406 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027406 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.027406 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14718.390884 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14718.390884 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42736.801593 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 42736.801593 # average WriteReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9929.233871 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9929.233871 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5495.306712 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5495.306712 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25956.534143 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 25956.534143 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25956.534143 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 25956.534143 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 376581 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 376581 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 263761 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 263761 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176647 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 176647 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9920 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9920 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7371 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 7371 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 440408 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 440408 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 440408 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 440408 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3349960502 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3349960502 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7149928209 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7149928209 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 78594000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 78594000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25787113 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25787113 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10499888711 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 10499888711 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10499888711 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 10499888711 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13764207250 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13764207250 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807935730 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807935730 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39572142980 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39572142980 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028061 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028061 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026482 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026482 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059606 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059606 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044304 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044304 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027406 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.027406 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027406 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.027406 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12700.742346 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12700.742346 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40475.797545 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40475.797545 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7922.782258 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7922.782258 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3498.455162 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3498.455162 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23841.276069 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23841.276069 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23841.276069 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23841.276069 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 5707792 # DTB read hits
|
|
system.cpu1.dtb.read_misses 3579 # DTB read misses
|
|
system.cpu1.dtb.write_hits 3874264 # DTB write hits
|
|
system.cpu1.dtb.write_misses 643 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 1989 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 150 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 5711371 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 3874907 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 9582056 # DTB hits
|
|
system.cpu1.dtb.misses 4222 # DTB misses
|
|
system.cpu1.dtb.accesses 9586278 # DTB accesses
|
|
system.cpu1.itb.inst_hits 19381456 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 2171 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 19383627 # ITB inst accesses
|
|
system.cpu1.itb.hits 19381456 # DTB hits
|
|
system.cpu1.itb.misses 2171 # DTB misses
|
|
system.cpu1.itb.accesses 19383627 # DTB accesses
|
|
system.cpu1.numCycles 2388389320 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.committedInsts 18800879 # Number of instructions committed
|
|
system.cpu1.committedOps 24908107 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 22271769 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 796713 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 2514831 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 22271769 # number of integer instructions
|
|
system.cpu1.num_fp_insts 6793 # number of float instructions
|
|
system.cpu1.num_int_register_reads 130796956 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 23323418 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written
|
|
system.cpu1.num_mem_refs 10017504 # number of memory refs
|
|
system.cpu1.num_load_insts 5984439 # Number of load instructions
|
|
system.cpu1.num_store_insts 4033065 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 1968748229.220572 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 419641090.779428 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.175700 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.824300 # Percentage of idle cycles
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 39064 # number of quiesce instructions executed
|
|
system.cpu1.icache.tags.replacements 376544 # number of replacements
|
|
system.cpu1.icache.tags.tagsinuse 474.938465 # Cycle average of tags in use
|
|
system.cpu1.icache.tags.total_refs 19004396 # Total number of references to valid blocks.
|
|
system.cpu1.icache.tags.sampled_refs 377056 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.tags.avg_refs 50.402052 # Average number of references to valid blocks.
|
|
system.cpu1.icache.tags.warmup_cycle 327017678500 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.938465 # Average occupied blocks per requestor
|
|
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927614 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_percent::total 0.927614 # Average percentage of cache occupancy
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 19004396 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 19004396 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 19004396 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 19004396 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 19004396 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 19004396 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 377056 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 377056 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 377056 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 377056 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 377056 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 377056 # number of overall misses
|
|
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5154731460 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_latency::total 5154731460 # number of ReadReq miss cycles
|
|
system.cpu1.icache.demand_miss_latency::cpu1.inst 5154731460 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_latency::total 5154731460 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.overall_miss_latency::cpu1.inst 5154731460 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_latency::total 5154731460 # number of overall miss cycles
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 19381452 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 19381452 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 19381452 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 19381452 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 19381452 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 19381452 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019454 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.019454 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019454 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.019454 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019454 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.019454 # miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13670.997040 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total 13670.997040 # average ReadReq miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13670.997040 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::total 13670.997040 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13670.997040 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::total 13670.997040 # average overall miss latency
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377056 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_misses::total 377056 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::cpu1.inst 377056 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::total 377056 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::cpu1.inst 377056 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::total 377056 # number of overall MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4398633040 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::total 4398633040 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4398633040 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::total 4398633040 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4398633040 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::total 4398633040 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6184500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6184500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6184500 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency::total 6184500 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019454 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019454 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019454 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::total 0.019454 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019454 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::total 0.019454 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11665.728804 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11665.728804 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11665.728804 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11665.728804 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11665.728804 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11665.728804 # average overall mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dcache.tags.replacements 220840 # number of replacements
|
|
system.cpu1.dcache.tags.tagsinuse 471.619758 # Cycle average of tags in use
|
|
system.cpu1.dcache.tags.total_refs 8232994 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.tags.sampled_refs 221207 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.tags.avg_refs 37.218506 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.tags.warmup_cycle 106228428000 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.619758 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.921132 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_percent::total 0.921132 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 4390579 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 4390579 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 3674302 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 3674302 # number of WriteReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 73464 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::total 73464 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 73742 # number of StoreCondReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::total 73742 # number of StoreCondReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 8064881 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 8064881 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 8064881 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 8064881 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 133951 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 133951 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 112879 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 112879 # number of WriteReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9745 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::total 9745 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9392 # number of StoreCondReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::total 9392 # number of StoreCondReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 246830 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 246830 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 246830 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 246830 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1653824236 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_latency::total 1653824236 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3737179210 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::total 3737179210 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 78087000 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::total 78087000 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49049473 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::total 49049473 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::cpu1.data 5391003446 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::total 5391003446 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::cpu1.data 5391003446 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::total 5391003446 # number of overall miss cycles
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 4524530 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 4524530 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 3787181 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 3787181 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 83209 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::total 83209 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 83134 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::total 83134 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 8311711 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 8311711 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 8311711 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 8311711 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029606 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.029606 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029806 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.029806 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117115 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117115 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.112974 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.112974 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029697 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.029697 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.029697 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.029697 # miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12346.486670 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12346.486670 # average ReadReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33107.834141 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total 33107.834141 # average WriteReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8013.032324 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8013.032324 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5222.473701 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5222.473701 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21840.957120 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::total 21840.957120 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21840.957120 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::total 21840.957120 # average overall miss latency
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.writebacks::writebacks 200060 # number of writebacks
|
|
system.cpu1.dcache.writebacks::total 200060 # number of writebacks
|
|
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133951 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_misses::total 133951 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 112879 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::total 112879 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9745 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9745 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9391 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::total 9391 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::cpu1.data 246830 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::total 246830 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 246830 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::total 246830 # number of overall MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1384995764 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1384995764 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3490409790 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3490409790 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58580000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 58580000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30268527 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30268527 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4875405554 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::total 4875405554 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4875405554 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::total 4875405554 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168372273000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168372273000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531015000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531015000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168903288000 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168903288000 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029606 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029606 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029806 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029806 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117115 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117115 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112962 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112962 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029697 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total 0.029697 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029697 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total 0.029697 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10339.570171 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10339.570171 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30921.693052 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30921.693052 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6011.287840 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6011.287840 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3223.142051 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3223.142051 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19752.078572 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19752.078572 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19752.078572 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19752.078572 # average overall mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.iocache.tags.replacements 0 # number of replacements
|
|
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 624927975253 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::total 624927975253 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 624927975253 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::total 624927975253 # number of overall MSHR uncacheable cycles
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|