1c321b8847
This patch changes the CoherentBus between the L1s and L2 to use the CPU clock and also four times the width compared to the default bus. The parameters are not intending to fit every single scenario, but rather serve as a better startingpoint than what we previously had. Note that the scripts that do not use the addTwoLevelCacheHiearchy are not affected by this change. A separate patch will update the stats.
89 lines
4.3 KiB
Python
89 lines
4.3 KiB
Python
# Copyright (c) 2010 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Lisa Hsu
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# Configure the M5 cache hierarchy config in one place
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#
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import m5
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from m5.objects import *
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from Caches import *
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from O3_ARM_v7a import *
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def config_cache(options, system):
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if options.l2cache:
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# Provide a clock for the L2 and the L1-to-L2 bus here as they
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# are not connected using addTwoLevelCacheHierarchy. Use the
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# same clock as the CPUs, and set the L1-to-L2 bus width to 32
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# bytes (256 bits).
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if options.cpu_type == "arm_detailed":
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system.l2 = O3_ARM_v7aL2(clock = options.clock,
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size = options.l2_size,
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assoc = options.l2_assoc,
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block_size=options.cacheline_size)
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else:
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system.l2 = L2Cache(clock = options.clock,
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size = options.l2_size,
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assoc = options.l2_assoc,
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block_size = options.cacheline_size)
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system.tol2bus = CoherentBus(clock = options.clock, width = 32)
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system.l2.cpu_side = system.tol2bus.master
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system.l2.mem_side = system.membus.slave
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for i in xrange(options.num_cpus):
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if options.caches:
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if options.cpu_type == "arm_detailed":
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icache = O3_ARM_v7a_ICache(size = options.l1i_size,
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assoc = options.l1i_assoc,
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block_size=options.cacheline_size)
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dcache = O3_ARM_v7a_DCache(size = options.l1d_size,
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assoc = options.l1d_assoc,
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block_size=options.cacheline_size)
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else:
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icache = L1Cache(size = options.l1i_size,
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assoc = options.l1i_assoc,
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block_size=options.cacheline_size)
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dcache = L1Cache(size = options.l1d_size,
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assoc = options.l1d_assoc,
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block_size=options.cacheline_size)
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# When connecting the caches, the clock is also inherited
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# from the CPU in question
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if buildEnv['TARGET_ISA'] == 'x86':
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system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
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PageTableWalkerCache(),
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PageTableWalkerCache())
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else:
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system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
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system.cpu[i].createInterruptController()
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if options.l2cache:
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system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
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else:
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system.cpu[i].connectAllPorts(system.membus)
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return system
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