72538294fb
This patch cleans up a number of minor issues aiming to get closer to compliance with the C++0x standard as interpreted by gcc and clang (compile with std=c++0x and -pedantic-errors). In particular, the patch cleans up enums where the last item was succeded by a comma, namespaces closed by a curcly brace followed by a semi-colon, and the use of the GNU-extension typeof (replaced by templated functions). It does not address variable-length arrays, zero-size arrays, anonymous structs, range expressions in switch statements, and the use of long long. The generated CPU code also has a large number of issues that remain to be fixed, mainly related to overflows in implicit constant conversion (due to shifts).
229 lines
8.2 KiB
C++
229 lines
8.2 KiB
C++
/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include "arch/arm/isa_traits.hh"
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#include "arch/arm/miscregs.hh"
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#include "arch/arm/nativetrace.hh"
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#include "cpu/thread_context.hh"
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#include "debug/ExecRegDelta.hh"
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#include "params/ArmNativeTrace.hh"
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#include "sim/byteswap.hh"
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namespace Trace {
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#if TRACING_ON
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static const char *regNames[] = {
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "fp", "r12", "sp", "lr", "pc",
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"cpsr", "f0", "f1", "f2", "f3", "f4", "f5", "f6",
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"f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14",
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"f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22",
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"f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30",
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"f31", "fpscr"
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};
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#endif
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void
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Trace::ArmNativeTrace::ThreadState::update(NativeTrace *parent)
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{
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oldState = state[current];
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current = (current + 1) % 2;
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newState = state[current];
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memcpy(newState, oldState, sizeof(state[0]));
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uint64_t diffVector;
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parent->read(&diffVector, sizeof(diffVector));
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diffVector = ArmISA::gtoh(diffVector);
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int changes = 0;
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for (int i = 0; i < STATE_NUMVALS; i++) {
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if (diffVector & 0x1) {
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changed[i] = true;
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changes++;
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} else {
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changed[i] = false;
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}
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diffVector >>= 1;
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}
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uint64_t values[changes];
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parent->read(values, sizeof(values));
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int pos = 0;
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for (int i = 0; i < STATE_NUMVALS; i++) {
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if (changed[i]) {
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newState[i] = ArmISA::gtoh(values[pos++]);
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changed[i] = (newState[i] != oldState[i]);
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}
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}
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}
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void
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Trace::ArmNativeTrace::ThreadState::update(ThreadContext *tc)
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{
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oldState = state[current];
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current = (current + 1) % 2;
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newState = state[current];
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// Regular int regs
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for (int i = 0; i < 15; i++) {
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newState[i] = tc->readIntReg(i);
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changed[i] = (oldState[i] != newState[i]);
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}
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//R15, aliased with the PC
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newState[STATE_PC] = tc->pcState().npc();
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changed[STATE_PC] = (newState[STATE_PC] != oldState[STATE_PC]);
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//CPSR
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CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
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cpsr.nz = tc->readIntReg(INTREG_CONDCODES_NZ);
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cpsr.c = tc->readIntReg(INTREG_CONDCODES_C);
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cpsr.v = tc->readIntReg(INTREG_CONDCODES_V);
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cpsr.ge = tc->readIntReg(INTREG_CONDCODES_GE);
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newState[STATE_CPSR] = cpsr;
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changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]);
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for (int i = 0; i < NumFloatArchRegs; i += 2) {
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newState[STATE_F0 + (i >> 1)] =
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static_cast<uint64_t>(tc->readFloatRegBits(i + 1)) << 32 |
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tc->readFloatRegBits(i);
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}
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newState[STATE_FPSCR] = tc->readMiscRegNoEffect(MISCREG_FPSCR) |
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tc->readIntReg(INTREG_FPCONDCODES);
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}
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void
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Trace::ArmNativeTrace::check(NativeTraceRecord *record)
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{
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ThreadContext *tc = record->getThread();
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// This area is read only on the target. It can't stop there to tell us
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// what's going on, so we should skip over anything there also.
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if (tc->nextInstAddr() > 0xffff0000)
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return;
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nState.update(this);
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mState.update(tc);
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// If a syscall just happened native trace needs another tick
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if ((mState.oldState[STATE_PC] == nState.oldState[STATE_PC]) &&
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(mState.newState[STATE_PC] - 4 == nState.newState[STATE_PC])) {
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DPRINTF(ExecRegDelta, "Advancing to match PCs after syscall\n");
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nState.update(this);
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}
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bool errorFound = false;
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// Regular int regs
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for (int i = 0; i < STATE_NUMVALS; i++) {
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if (nState.changed[i] || mState.changed[i]) {
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bool oldMatch = (mState.oldState[i] == nState.oldState[i]);
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bool newMatch = (mState.newState[i] == nState.newState[i]);
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if (oldMatch && newMatch) {
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// The more things change, the more they stay the same.
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continue;
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}
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errorFound = true;
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#ifndef NDEBUG
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const char *vergence = " ";
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if (oldMatch && !newMatch) {
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vergence = "<>";
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} else if (!oldMatch && newMatch) {
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vergence = "><";
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}
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if (!nState.changed[i]) {
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DPRINTF(ExecRegDelta, "%s [%5s] "\
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"Native: %#010x "\
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"M5: %#010x => %#010x\n",
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vergence, regNames[i],
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nState.newState[i],
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mState.oldState[i], mState.newState[i]);
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} else if (!mState.changed[i]) {
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DPRINTF(ExecRegDelta, "%s [%5s] "\
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"Native: %#010x => %#010x "\
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"M5: %#010x \n",
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vergence, regNames[i],
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nState.oldState[i], nState.newState[i],
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mState.newState[i]);
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} else {
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DPRINTF(ExecRegDelta, "%s [%5s] "\
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"Native: %#010x => %#010x "\
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"M5: %#010x => %#010x\n",
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vergence, regNames[i],
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nState.oldState[i], nState.newState[i],
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mState.oldState[i], mState.newState[i]);
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}
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#endif
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}
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}
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if (errorFound) {
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StaticInstPtr inst = record->getStaticInst();
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assert(inst);
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bool ran = true;
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if (inst->isMicroop()) {
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ran = false;
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inst = record->getMacroStaticInst();
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}
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assert(inst);
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record->traceInst(inst, ran);
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bool pcError = (mState.newState[STATE_PC] !=
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nState.newState[STATE_PC]);
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if (stopOnPCError && pcError)
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panic("Native trace detected an error in control flow!");
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}
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}
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} // namespace Trace
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////////////////////////////////////////////////////////////////////////
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//
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// ExeTracer Simulation Object
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//
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Trace::ArmNativeTrace *
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ArmNativeTraceParams::create()
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{
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return new Trace::ArmNativeTrace(this);
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}
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