457 lines
51 KiB
Text
457 lines
51 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 72923 # Simulator instruction rate (inst/s)
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host_mem_usage 204488 # Number of bytes of host memory used
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host_seconds 0.07 # Real time elapsed on the host
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host_tick_rate 179666090 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 5169 # Number of instructions simulated
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sim_seconds 0.000013 # Number of seconds simulated
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sim_ticks 12784500 # Number of ticks simulated
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.BTBHits 538 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 1522 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 378 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 1192 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 1744 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 215 # Number of times the RAS was used to get a target.
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system.cpu.commit.COM:branches 916 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 76 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle::samples 12273 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::mean 0.474701 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::stdev 1.213395 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::0 9782 79.70% 79.70% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1 1006 8.20% 87.90% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2 705 5.74% 93.64% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3 340 2.77% 96.41% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4 169 1.38% 97.79% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5 96 0.78% 98.57% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::6 67 0.55% 99.12% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::7 32 0.26% 99.38% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::8 76 0.62% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::total 12273 # Number of insts commited each cycle
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system.cpu.commit.COM:count 5826 # Number of instructions committed
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system.cpu.commit.COM:loads 1164 # Number of loads committed
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs 2089 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 3481 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 5169 # Number of Instructions Simulated
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system.cpu.committedInsts_total 5169 # Number of Instructions Simulated
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system.cpu.cpi 4.946798 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 4.946798 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 1824 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 36046.875000 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35938.888889 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 1696 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 4614000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.070175 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 128 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 38 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 3234500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.049342 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 90 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 34184.971098 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36196.078431 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 579 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 11828000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.374054 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 346 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 295 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 1846000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 16.134752 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 2749 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 34687.763713 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 36031.914894 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 2275 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 16442000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.172426 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 474 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 333 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 5080500 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.051291 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 141 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.occ_%::0 0.022390 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 91.708831 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 2749 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 34687.763713 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 36031.914894 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 2275 # number of overall hits
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system.cpu.dcache.overall_miss_latency 16442000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.172426 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 474 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 333 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 5080500 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.051291 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 141 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 91.708831 # Cycle average of tags in use
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system.cpu.dcache.total_refs 2275 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 0 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 736 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 42 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 88 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 10461 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 8771 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 2729 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 649 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 153 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 37 # Number of cycles decode is unblocking
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.fetch.Branches 1744 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 1555 # Number of cache lines fetched
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system.cpu.fetch.Cycles 4407 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 219 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 11052 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 393 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.068205 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 1555 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 753 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 0.432225 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist::samples 12922 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 0.855286 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.122030 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 10085 78.05% 78.05% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 1182 9.15% 87.19% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 138 1.07% 88.26% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 127 0.98% 89.24% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 278 2.15% 91.39% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 124 0.96% 92.35% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 162 1.25% 93.61% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 99 0.77% 94.37% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 727 5.63% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 12922 # Number of instructions fetched each cycle (Total)
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system.cpu.icache.ReadReq_accesses 1555 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 36274.074074 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 35024.316109 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 1150 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 14691000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.260450 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 405 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 76 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 11523000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.211576 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 329 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 3.495441 # Average number of references to valid blocks.
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 1555 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 36274.074074 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 35024.316109 # average overall mshr miss latency
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system.cpu.icache.demand_hits 1150 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 14691000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.260450 # miss rate for demand accesses
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system.cpu.icache.demand_misses 405 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 76 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 11523000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.211576 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 329 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.occ_%::0 0.077565 # Average percentage of cache occupancy
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system.cpu.icache.occ_blocks::0 158.853467 # Average occupied blocks per context
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system.cpu.icache.overall_accesses 1555 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 36274.074074 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 35024.316109 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 1150 # number of overall hits
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system.cpu.icache.overall_miss_latency 14691000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.260450 # miss rate for overall accesses
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system.cpu.icache.overall_misses 405 # number of overall misses
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system.cpu.icache.overall_mshr_hits 76 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 11523000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.211576 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 329 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 15 # number of replacements
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system.cpu.icache.sampled_refs 329 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 158.853467 # Cycle average of tags in use
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system.cpu.icache.total_refs 1150 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idleCycles 12648 # Total number of cycles that the CPU has spent unscheduled due to idling
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system.cpu.iew.EXEC:branches 1183 # Number of branches executed
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system.cpu.iew.EXEC:nop 1244 # number of nop insts executed
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system.cpu.iew.EXEC:rate 0.279625 # Inst execution rate
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system.cpu.iew.EXEC:refs 2950 # number of memory reference insts executed
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system.cpu.iew.EXEC:stores 1042 # Number of stores executed
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system.cpu.iew.EXEC:swp 0 # number of swp insts executed
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system.cpu.iew.WB:consumers 3586 # num instructions consuming a value
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system.cpu.iew.WB:count 6793 # cumulative count of insts written-back
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system.cpu.iew.WB:fanout 0.717513 # average fanout of values written-back
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system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
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system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.iew.WB:producers 2573 # num instructions producing a value
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system.cpu.iew.WB:rate 0.265663 # insts written-back per cycle
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system.cpu.iew.WB:sent 6861 # cumulative count of insts sent to commit
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system.cpu.iew.branchMispredicts 377 # Number of branch mispredicts detected at execute
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system.cpu.iew.iewBlockCycles 165 # Number of cycles IEW is blocking
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system.cpu.iew.iewDispLoadInsts 2139 # Number of dispatched load instructions
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system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions
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system.cpu.iew.iewDispSquashedInsts 207 # Number of squashed instructions skipped by dispatch
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system.cpu.iew.iewDispStoreInsts 1135 # Number of dispatched store instructions
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system.cpu.iew.iewDispatchedInsts 9313 # Number of instructions dispatched to IQ
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system.cpu.iew.iewExecLoadInsts 1908 # Number of load instructions executed
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system.cpu.iew.iewExecSquashedInsts 223 # Number of squashed instructions skipped in execute
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system.cpu.iew.iewExecutedInsts 7150 # Number of executed instructions
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system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
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system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall
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system.cpu.iew.iewSquashCycles 649 # Number of cycles IEW is squashing
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system.cpu.iew.iewUnblockCycles 14 # Number of cycles IEW is unblocking
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system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
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system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
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system.cpu.iew.lsq.thread.0.forwLoads 66 # Number of loads that had data forwarded from stores
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system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
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system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
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system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
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system.cpu.iew.lsq.thread.0.memOrderViolation 16 # Number of memory ordering violations
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system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 975 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread.0.squashedStores 210 # Number of stores squashed
|
|
system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations
|
|
system.cpu.iew.predictedNotTakenIncorrect 259 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.ipc 0.202151 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.202151 # IPC: Total IPC of All Threads
|
|
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IntAlu 4328 58.70% 58.70% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IntMult 4 0.05% 58.75% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.03% 58.78% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.03% 58.81% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.81% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.81% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.81% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.81% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.81% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 58.81% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 58.81% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 58.81% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 58.81% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 58.81% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 58.81% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 58.81% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 58.81% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 58.81% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 58.81% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 58.81% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 58.81% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 58.81% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 58.81% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 58.81% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 58.81% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 58.81% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 58.81% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 58.81% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 58.81% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::MemRead 1984 26.91% 85.72% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1053 14.28% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::total 7373 # Type of FU issued
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 142 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.019259 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IntAlu 7 4.93% 4.93% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 4.93% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 4.93% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 4.93% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 4.93% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 4.93% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 4.93% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 4.93% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 4.93% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 4.93% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 4.93% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 4.93% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 4.93% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 4.93% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 4.93% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 4.93% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 4.93% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 4.93% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 4.93% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 4.93% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 4.93% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 4.93% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 4.93% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 4.93% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 4.93% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 4.93% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 4.93% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 4.93% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 4.93% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::MemRead 83 58.45% 63.38% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::MemWrite 52 36.62% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:issued_per_cycle::samples 12922 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.570577 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.213210 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::0 9579 74.13% 74.13% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::1 1454 11.25% 85.38% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::2 793 6.14% 91.52% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::3 511 3.95% 95.47% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::4 304 2.35% 97.83% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::5 160 1.24% 99.06% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::6 76 0.59% 99.65% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::7 32 0.25% 99.90% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::8 13 0.10% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::total 12922 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:rate 0.288346 # Inst issue rate
|
|
system.cpu.iq.iqInstsAdded 8058 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 7373 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 2456 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 1522 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34696.078431 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31490.196078 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_miss_latency 1769500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1606000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_accesses 419 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34325.721154 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31134.615385 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_miss_latency 14279500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.992840 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_misses 416 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 12952000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992840 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_misses 416 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_refs 0.007212 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.demand_accesses 470 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_avg_miss_latency 34366.167024 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31173.447537 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_miss_latency 16049000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_rate 0.993617 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_misses 467 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_miss_latency 14558000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.993617 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_misses 467 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.occ_%::0 0.006661 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_blocks::0 218.261856 # Average occupied blocks per context
|
|
system.cpu.l2cache.overall_accesses 470 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_avg_miss_latency 34366.167024 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31173.447537 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_hits 3 # number of overall hits
|
|
system.cpu.l2cache.overall_miss_latency 16049000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_rate 0.993617 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses 467 # number of overall misses
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_miss_latency 14558000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.993617 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_misses 467 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.sampled_refs 416 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.tagsinuse 218.261856 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores.
|
|
system.cpu.memDep0.insertedLoads 2139 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 1135 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.numCycles 25570 # number of cpu cycles simulated
|
|
system.cpu.rename.RENAME:BlockCycles 238 # Number of cycles rename is blocking
|
|
system.cpu.rename.RENAME:CommittedMaps 3410 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:IdleCycles 8931 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 71 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:RenameLookups 12088 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 10031 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 6119 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 2609 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 649 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:UnblockCycles 81 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 2709 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:serializeStallCycles 414 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 16 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 196 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 11 # count of temporary serializing insts renamed
|
|
system.cpu.timesIdled 259 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|