gem5/src/arch/sparc/isa
2010-05-14 14:22:51 -07:00
..
formats SPARC: Adjust a few instructions to not write registers in initiateAcc. 2009-02-25 10:16:04 -08:00
base.isa String constant const-ness changes to placate g++ 4.2. 2007-10-31 18:04:22 -07:00
bitfields.isa add pseduo instruction support for sparc 2007-02-21 21:06:17 -05:00
decoder.isa SPARC: Implement the version of movcc that uses the fp condition codes. 2010-05-14 14:22:51 -07:00
includes.isa Registers: Add a registers.hh file as an ISA switched header. 2009-07-08 23:02:21 -07:00
main.isa Broke Load/Store instructions into microcode, and partially refactored memory operations in the SPARC ISA description. 2006-10-23 07:55:52 -04:00
operands.isa Make the GSR into a renamed control register. It should be split into a renamed part and a control part for the different bitfields, but the renamed part is all that's actually used. 2007-04-22 17:43:45 +00:00