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gem5/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
Steve Reinhardt 89ea323250 Update stats for new prefetching fixes. 
Prefetching is not enabled in any of our regressions, so no significant
stat values have changed, but zero-valued prefetch stats no longer
show up when prefetching is disabled so there are noticable changes
in the reference stat files anyway.
2009-02-16 12:09:45 -05:00

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---------- Begin Simulation Statistics ----------
host_inst_rate 1421036 # Simulator instruction rate (inst/s)
host_mem_usage 208620 # Number of bytes of host memory used
host_seconds 1052.39 # Real time elapsed on the host
host_tick_rate 2272325062 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1495482356 # Number of instructions simulated
sim_seconds 2.391370 # Number of seconds simulated
sim_ticks 2391369984000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 384102182 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 24147.662775 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21147.661617 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 382375369 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 41698498000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.004496 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1726813 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 36518057000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.004496 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1726813 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 149160200 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 55999.912355 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.912355 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 147694052 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 82104159500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.009829 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1466148 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 77705715500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009829 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1466148 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 210.782575 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 533262382 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 38773.620317 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 35773.619690 # average overall mshr miss latency
system.cpu.dcache.demand_hits 530069421 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 123802657500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.005988 # miss rate for demand accesses
system.cpu.dcache.demand_misses 3192961 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 114223772500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.005988 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 3192961 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 533262382 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 38773.620317 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35773.619690 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 530069421 # number of overall hits
system.cpu.dcache.overall_miss_latency 123802657500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.005988 # miss rate for overall accesses
system.cpu.dcache.overall_misses 3192961 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 114223772500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.005988 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 3192961 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 2513875 # number of replacements
system.cpu.dcache.sampled_refs 2517971 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4086.151068 # Cycle average of tags in use
system.cpu.dcache.total_refs 530744411 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 12270576000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 1463913 # number of writebacks
system.cpu.icache.ReadReq_accesses 1737364550 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 48415.215073 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 45415.215073 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 1737361737 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 136192000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 2813 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 127753000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 2813 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 617618.818699 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 1737364550 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 48415.215073 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency
system.cpu.icache.demand_hits 1737361737 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 136192000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses
system.cpu.icache.demand_misses 2813 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 127753000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 2813 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 1737364550 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 48415.215073 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 1737361737 # number of overall hits
system.cpu.icache.overall_miss_latency 136192000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses
system.cpu.icache.overall_misses 2813 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 127753000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 2813 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 1253 # number of replacements
system.cpu.icache.sampled_refs 2813 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 873.846977 # Cycle average of tags in use
system.cpu.icache.total_refs 1737361737 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses 791158 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.014536 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 41140227500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 791158 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 31646320000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 791158 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 1729626 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 1310104 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 21815144000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.242551 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 419522 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 16780880000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.242551 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 419522 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 674990 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51989.214655 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 35092200000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 674990 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 26999600000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 674990 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 1463913 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 1463913 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 3.428071 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 2520784 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000.009499 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 1310104 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 62955371500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.480279 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 1210680 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 48427200000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.480279 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 1210680 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 2520784 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000.009499 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 1310104 # number of overall hits
system.cpu.l2cache.overall_miss_latency 62955371500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.480279 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 1210680 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 48427200000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.480279 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 1210680 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 663512 # number of replacements
system.cpu.l2cache.sampled_refs 679920 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 17171.685875 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2330814 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 1313098367000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 481430 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 4782739968 # number of cpu cycles simulated
system.cpu.num_insts 1495482356 # Number of instructions executed
system.cpu.num_refs 533548971 # Number of memory references
system.cpu.workload.PROG:num_syscalls 551 # Number of system calls
---------- End Simulation Statistics ----------
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