3051 lines
364 KiB
Text
3051 lines
364 KiB
Text
|
|
---------- Begin Simulation Statistics ----------
|
|
sim_seconds 2.871850 # Number of seconds simulated
|
|
sim_ticks 2871850306000 # Number of ticks simulated
|
|
final_tick 2871850306000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
host_inst_rate 595194 # Simulator instruction rate (inst/s)
|
|
host_op_rate 719909 # Simulator op (including micro ops) rate (op/s)
|
|
host_tick_rate 12993896386 # Simulator tick rate (ticks/s)
|
|
host_mem_usage 612660 # Number of bytes of host memory used
|
|
host_seconds 221.02 # Real time elapsed on the host
|
|
sim_insts 131546959 # Number of instructions simulated
|
|
sim_ops 159110973 # Number of ops (including micro ops) simulated
|
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
|
system.clk_domain.clock 1000 # Clock period in ticks
|
|
system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu0.inst 1178404 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu0.data 1267556 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu0.l2cache.prefetcher 8608576 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu1.inst 129300 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu1.data 549908 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu1.l2cache.prefetcher 341632 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::total 12076912 # Number of bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu0.inst 1178404 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu1.inst 129300 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::total 1307704 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_written::writebacks 8530240 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::total 8547804 # Number of bytes written to this memory
|
|
system.physmem.num_reads::cpu0.dtb.walker 6 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu0.inst 26866 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu0.data 20325 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu0.l2cache.prefetcher 134509 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu1.inst 2175 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu1.data 8613 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu1.l2cache.prefetcher 5338 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::total 197850 # Number of read requests responded to by this memory
|
|
system.physmem.num_writes::writebacks 133285 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::total 137676 # Number of write requests responded to by this memory
|
|
system.physmem.bw_read::cpu0.dtb.walker 134 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu0.inst 410329 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu0.data 441373 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu0.l2cache.prefetcher 2997571 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu1.inst 45023 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu1.data 191482 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu1.l2cache.prefetcher 118959 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::total 4205272 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu0.inst 410329 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu1.inst 45023 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::total 455352 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::writebacks 2970294 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::cpu0.data 6102 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::total 2976410 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_total::writebacks 2970294 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu0.dtb.walker 134 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu0.inst 410329 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu0.data 447475 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu0.l2cache.prefetcher 2997571 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu1.inst 45023 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu1.data 191496 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu1.l2cache.prefetcher 118959 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::total 7181682 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.readReqs 197850 # Number of read requests accepted
|
|
system.physmem.writeReqs 137676 # Number of write requests accepted
|
|
system.physmem.readBursts 197850 # Number of DRAM read bursts, including those serviced by the write queue
|
|
system.physmem.writeBursts 137676 # Number of DRAM write bursts, including those merged in the write queue
|
|
system.physmem.bytesReadDRAM 12652352 # Total number of bytes read from DRAM
|
|
system.physmem.bytesReadWrQ 10048 # Total number of bytes read from write queue
|
|
system.physmem.bytesWritten 8560960 # Total number of bytes written to DRAM
|
|
system.physmem.bytesReadSys 12076912 # Total read bytes from the system interface side
|
|
system.physmem.bytesWrittenSys 8547804 # Total written bytes from the system interface side
|
|
system.physmem.servicedByWrQ 157 # Number of DRAM read bursts serviced by the write queue
|
|
system.physmem.mergedWrBursts 3895 # Number of DRAM write bursts merged with an existing one
|
|
system.physmem.neitherReadNorWriteReqs 64578 # Number of requests that are neither read nor write
|
|
system.physmem.perBankRdBursts::0 11583 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::1 11800 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::2 11971 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::3 11847 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::4 20098 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::5 11961 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::6 12460 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::7 12487 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::8 11821 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::9 12495 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::10 11828 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::11 11338 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::12 11476 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::13 11922 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::14 11270 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::15 11336 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::0 8288 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::1 8566 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::2 8821 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::3 8522 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::4 7854 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::5 8398 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::6 8910 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::7 8793 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::8 8333 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::9 8912 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::10 8495 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::11 8357 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::12 8083 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::13 7998 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::14 7822 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::15 7613 # Per bank write bursts
|
|
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
|
system.physmem.numWrRetry 27 # Number of times write queue was full causing retry
|
|
system.physmem.totGap 2871849883000 # Total gap between requests
|
|
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::2 9732 # Read request sizes (log2)
|
|
system.physmem.readPktSize::3 28 # Read request sizes (log2)
|
|
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::6 188090 # Read request sizes (log2)
|
|
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::2 4391 # Write request sizes (log2)
|
|
system.physmem.writePktSize::3 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::6 133285 # Write request sizes (log2)
|
|
system.physmem.rdQLenPdf::0 138613 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::1 15680 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::2 10206 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::3 8777 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::4 7036 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::5 5467 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::6 4577 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::7 3802 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::8 3339 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::9 81 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::10 56 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::11 33 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::12 15 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::15 2732 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::16 3200 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::17 4416 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::18 5092 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::19 6151 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::20 6617 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::21 7823 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::22 7841 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::23 8781 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::24 8913 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::25 9011 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::26 10422 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::27 8444 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::28 8402 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 9645 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::30 8273 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::31 7347 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::32 6958 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::33 367 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::34 363 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::35 241 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::36 219 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::37 186 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::38 194 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::39 130 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::40 122 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::41 115 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::42 142 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::43 110 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::44 133 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::45 118 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::46 98 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::48 126 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::49 127 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::50 101 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::51 77 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::53 93 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::54 47 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::55 31 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 42 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 36 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 53 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 32 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 50 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 33 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::62 30 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::63 80 # What write queue length does an incoming req see
|
|
system.physmem.bytesPerActivate::samples 87676 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::mean 241.950454 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::gmean 136.764211 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::stdev 303.933653 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::0-127 46396 52.92% 52.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::128-255 17641 20.12% 73.04% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::256-383 5908 6.74% 79.78% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::384-511 3515 4.01% 83.79% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::512-639 2504 2.86% 86.64% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::640-767 1565 1.78% 88.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-895 855 0.98% 89.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-1023 945 1.08% 90.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1151 8347 9.52% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 87676 # Bytes accessed per row activation
|
|
system.physmem.rdPerTurnAround::samples 6535 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::mean 30.251262 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::stdev 585.438505 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::0-2047 6533 99.97% 99.97% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 6535 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 6535 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::mean 20.469013 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::gmean 18.883832 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::stdev 12.598321 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16-19 5330 81.56% 81.56% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20-23 483 7.39% 88.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24-27 73 1.12% 90.07% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28-31 153 2.34% 92.41% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-35 33 0.50% 92.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::36-39 123 1.88% 94.80% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-43 36 0.55% 95.35% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::44-47 26 0.40% 95.75% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48-51 25 0.38% 96.13% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::52-55 15 0.23% 96.36% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-59 6 0.09% 96.45% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::60-63 6 0.09% 96.54% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-67 152 2.33% 98.87% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::68-71 6 0.09% 98.96% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-75 2 0.03% 98.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::76-79 26 0.40% 99.39% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-83 7 0.11% 99.50% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::84-87 1 0.02% 99.51% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::88-91 1 0.02% 99.53% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::92-95 2 0.03% 99.56% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::100-103 2 0.03% 99.59% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::104-107 2 0.03% 99.62% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::112-115 1 0.02% 99.63% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::116-119 1 0.02% 99.65% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::124-127 2 0.03% 99.68% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-131 13 0.20% 99.88% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::140-143 3 0.05% 99.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::152-155 1 0.02% 99.94% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::156-159 2 0.03% 99.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::244-247 1 0.02% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 6535 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 4503336233 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 8210079983 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 988465000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 22779.44 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 41529.44 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 4.41 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 2.98 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 4.21 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 2.98 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.06 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 22.35 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 165103 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 78678 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 83.51 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 58.81 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 8559246.92 # Average gap between requests
|
|
system.physmem.pageHitRate 73.54 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 341250840 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 186198375 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 812814600 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 441624960 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 187575236160 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 85820448015 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 1647828636000 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 1923006208950 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 669.605484 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 2741162536487 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 95897360000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 34789668513 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 321579720 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 175465125 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 729183000 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 425172240 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 187575236160 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 84866434740 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 1648665489750 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 1922758560735 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 669.519251 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 2742561244982 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 95897360000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 33391555518 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s)
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.dtb.walker.walks 8830 # Table walker walks requested
|
|
system.cpu0.dtb.walker.walksShort 8830 # Table walker walks initiated with short descriptors
|
|
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1617 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 7213 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu0.dtb.walker.walkWaitTime::samples 8830 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::0 8830 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::total 8830 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::samples 7312 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::mean 12253.145514 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::gmean 11429.774492 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::stdev 6252.045789 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::0-32767 7284 99.62% 99.62% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::32768-65535 24 0.33% 99.95% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::131072-163839 3 0.04% 99.99% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::total 7312 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walksPending::samples 1809726500 # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::0 1809726500 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::total 1809726500 # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walkPageSizes::4K 5742 78.53% 78.53% # Table walker page sizes translated
|
|
system.cpu0.dtb.walker.walkPageSizes::1M 1570 21.47% 100.00% # Table walker page sizes translated
|
|
system.cpu0.dtb.walker.walkPageSizes::total 7312 # Table walker page sizes translated
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 8830 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 8830 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7312 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7312 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin::total 16142 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dtb.read_hits 25809403 # DTB read hits
|
|
system.cpu0.dtb.read_misses 7606 # DTB read misses
|
|
system.cpu0.dtb.write_hits 19327142 # DTB write hits
|
|
system.cpu0.dtb.write_misses 1224 # DTB write misses
|
|
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
|
|
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dtb.flush_entries 3761 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dtb.prefetch_faults 1861 # Number of TLB faults due to prefetch
|
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dtb.perms_faults 321 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dtb.read_accesses 25817009 # DTB read accesses
|
|
system.cpu0.dtb.write_accesses 19328366 # DTB write accesses
|
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dtb.hits 45136545 # DTB hits
|
|
system.cpu0.dtb.misses 8830 # DTB misses
|
|
system.cpu0.dtb.accesses 45145375 # DTB accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.itb.walker.walks 3674 # Table walker walks requested
|
|
system.cpu0.itb.walker.walksShort 3674 # Table walker walks initiated with short descriptors
|
|
system.cpu0.itb.walker.walksShortTerminationLevel::Level1 320 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3354 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu0.itb.walker.walkWaitTime::samples 3674 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkWaitTime::0 3674 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkWaitTime::total 3674 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::samples 2576 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::mean 12688.276398 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::gmean 11839.861434 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::stdev 6240.244766 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::0-16383 2261 87.77% 87.77% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::16384-32767 282 10.95% 98.72% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::32768-49151 30 1.16% 99.88% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.04% 99.92% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::163840-180223 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::total 2576 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walksPending::samples 1809154500 # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walksPending::0 1809154500 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walksPending::total 1809154500 # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walkPageSizes::4K 2256 87.58% 87.58% # Table walker page sizes translated
|
|
system.cpu0.itb.walker.walkPageSizes::1M 320 12.42% 100.00% # Table walker page sizes translated
|
|
system.cpu0.itb.walker.walkPageSizes::total 2576 # Table walker page sizes translated
|
|
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3674 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3674 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2576 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2576 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin::total 6250 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.inst_hits 121850168 # ITB inst hits
|
|
system.cpu0.itb.inst_misses 3674 # ITB inst misses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
|
|
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
|
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.itb.flush_entries 2371 # Number of entries that have been flushed from TLB
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.inst_accesses 121853842 # ITB inst accesses
|
|
system.cpu0.itb.hits 121850168 # DTB hits
|
|
system.cpu0.itb.misses 3674 # DTB misses
|
|
system.cpu0.itb.accesses 121853842 # DTB accesses
|
|
system.cpu0.numCycles 5743700612 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 1892 # number of quiesce instructions executed
|
|
system.cpu0.committedInsts 118029542 # Number of instructions committed
|
|
system.cpu0.committedOps 142673635 # Number of ops (including micro ops) committed
|
|
system.cpu0.num_int_alu_accesses 126253590 # Number of integer alu accesses
|
|
system.cpu0.num_fp_alu_accesses 11483 # Number of float alu accesses
|
|
system.cpu0.num_func_calls 12792333 # number of times a function call or return occured
|
|
system.cpu0.num_conditional_control_insts 16043976 # number of instructions that are conditional controls
|
|
system.cpu0.num_int_insts 126253590 # number of integer instructions
|
|
system.cpu0.num_fp_insts 11483 # number of float instructions
|
|
system.cpu0.num_int_register_reads 232324144 # number of times the integer registers were read
|
|
system.cpu0.num_int_register_writes 87654298 # number of times the integer registers were written
|
|
system.cpu0.num_fp_register_reads 8771 # number of times the floating registers were read
|
|
system.cpu0.num_fp_register_writes 2716 # number of times the floating registers were written
|
|
system.cpu0.num_cc_register_reads 516734560 # number of times the CC registers were read
|
|
system.cpu0.num_cc_register_writes 53610723 # number of times the CC registers were written
|
|
system.cpu0.num_mem_refs 46299073 # number of memory refs
|
|
system.cpu0.num_load_insts 26069844 # Number of load instructions
|
|
system.cpu0.num_store_insts 20229229 # Number of store instructions
|
|
system.cpu0.num_idle_cycles 5455076908.366100 # Number of idle cycles
|
|
system.cpu0.num_busy_cycles 288623703.633900 # Number of busy cycles
|
|
system.cpu0.not_idle_fraction 0.050250 # Percentage of non-idle cycles
|
|
system.cpu0.idle_fraction 0.949750 # Percentage of idle cycles
|
|
system.cpu0.Branches 29603215 # Number of branches fetched
|
|
system.cpu0.op_class::No_OpClass 2315 0.00% 0.00% # Class of executed instruction
|
|
system.cpu0.op_class::IntAlu 100054313 68.31% 68.31% # Class of executed instruction
|
|
system.cpu0.op_class::IntMult 112340 0.08% 68.39% # Class of executed instruction
|
|
system.cpu0.op_class::IntDiv 0 0.00% 68.39% # Class of executed instruction
|
|
system.cpu0.op_class::FloatAdd 0 0.00% 68.39% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCmp 0 0.00% 68.39% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCvt 0 0.00% 68.39% # Class of executed instruction
|
|
system.cpu0.op_class::FloatMult 0 0.00% 68.39% # Class of executed instruction
|
|
system.cpu0.op_class::FloatDiv 0 0.00% 68.39% # Class of executed instruction
|
|
system.cpu0.op_class::FloatSqrt 0 0.00% 68.39% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAdd 0 0.00% 68.39% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAddAcc 0 0.00% 68.39% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAlu 0 0.00% 68.39% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCmp 0 0.00% 68.39% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCvt 0 0.00% 68.39% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMisc 0 0.00% 68.39% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMult 0 0.00% 68.39% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMultAcc 0 0.00% 68.39% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShift 0 0.00% 68.39% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.39% # Class of executed instruction
|
|
system.cpu0.op_class::SimdSqrt 0 0.00% 68.39% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.39% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.39% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.39% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.39% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.39% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMisc 8369 0.01% 68.39% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMult 0 0.00% 68.39% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.39% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.39% # Class of executed instruction
|
|
system.cpu0.op_class::MemRead 26069844 17.80% 86.19% # Class of executed instruction
|
|
system.cpu0.op_class::MemWrite 20229229 13.81% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::total 146476410 # Class of executed instruction
|
|
system.cpu0.dcache.tags.replacements 740882 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 488.760528 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 44216040 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 741394 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 59.639058 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 1836359000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 488.760528 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.954610 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.954610 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 90957934 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 90957934 # Number of data accesses
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 24496228 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 24496228 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 18570022 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 18570022 # number of WriteReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 327271 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::total 327271 # number of SoftPFReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374846 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 374846 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 372508 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 372508 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 43066250 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 43066250 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 43393521 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 43393521 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 423502 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 423502 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 340254 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 340254 # number of WriteReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 133712 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::total 133712 # number of SoftPFReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22535 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 22535 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19849 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 19849 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 763756 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 763756 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 897468 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 897468 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5717292500 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 5717292500 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6989183500 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 6989183500 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 344979500 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 344979500 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 511150000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 511150000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1456500 # number of StoreCondFailReq miss cycles
|
|
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1456500 # number of StoreCondFailReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 12706476000 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 12706476000 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 12706476000 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 12706476000 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 24919730 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 24919730 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 18910276 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 18910276 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 460983 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::total 460983 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 397381 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 397381 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 392357 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 392357 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 43830006 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 43830006 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 44290989 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 44290989 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016995 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.016995 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017993 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.017993 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.290058 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.290058 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056709 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056709 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.050589 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.050589 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.017425 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.017425 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.020263 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.020263 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13500.036600 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13500.036600 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20541.076666 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 20541.076666 # average WriteReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15308.608831 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15308.608831 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25751.927049 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25751.927049 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
|
|
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16636.826421 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 16636.826421 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14158.138229 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 14158.138229 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 740882 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 740882 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25304 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 25304 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15852 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15852 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu0.data 25304 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 25304 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu0.data 25304 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 25304 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 398198 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 398198 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 340254 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 340254 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 106613 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::total 106613 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6683 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6683 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19849 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 19849 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 738452 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 738452 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 845065 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 845065 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31860 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31860 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28553 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28553 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60413 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60413 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4887280000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4887280000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6648929500 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6648929500 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1745313500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1745313500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 102495000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102495000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 491343000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 491343000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1414500 # number of StoreCondFailReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1414500 # number of StoreCondFailReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11536209500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 11536209500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13281523000 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 13281523000 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6641550500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6641550500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5414724500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5414724500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12056275000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12056275000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015979 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015979 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017993 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017993 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.231273 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.231273 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016818 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016818 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.050589 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.050589 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016848 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.016848 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019080 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.019080 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12273.492082 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12273.492082 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19541.076666 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19541.076666 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16370.550496 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16370.550496 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15336.675146 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15336.675146 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24754.043025 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24754.043025 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15622.152151 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15622.152151 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15716.569731 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15716.569731 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208460.467671 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208460.467671 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189637.673800 # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189637.673800 # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199564.249417 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199564.249417 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.icache.tags.replacements 1154605 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 511.321447 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 120695042 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 1155117 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 104.487287 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 14862010000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.321447 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998675 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.998675 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 244855462 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 244855462 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 120695042 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 120695042 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 120695042 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 120695042 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 120695042 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 120695042 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 1155126 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 1155126 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 1155126 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 1155126 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 1155126 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 1155126 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12352499000 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 12352499000 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 12352499000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 12352499000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 12352499000 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 12352499000 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 121850168 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 121850168 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 121850168 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 121850168 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 121850168 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 121850168 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009480 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.009480 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009480 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.009480 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009480 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.009480 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10693.637750 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 10693.637750 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10693.637750 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 10693.637750 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10693.637750 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 10693.637750 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.writebacks::writebacks 1154605 # number of writebacks
|
|
system.cpu0.icache.writebacks::total 1154605 # number of writebacks
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1155126 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 1155126 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 1155126 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 1155126 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 1155126 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 1155126 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
|
|
system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11774936000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 11774936000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11774936000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 11774936000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11774936000 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 11774936000 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1253876500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::total 1253876500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009480 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009480 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009480 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.009480 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009480 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.009480 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10193.637750 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10193.637750 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10193.637750 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10193.637750 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10193.637750 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10193.637750 # average overall mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138979.882509 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average overall mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509 # average overall mshr uncacheable latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.l2cache.prefetcher.num_hwpf_issued 1946486 # number of hwpf issued
|
|
system.cpu0.l2cache.prefetcher.pfIdentified 1946511 # number of prefetch candidates identified
|
|
system.cpu0.l2cache.prefetcher.pfBufferHit 22 # number of redundant prefetches already in prefetch queue
|
|
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
|
|
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
|
|
system.cpu0.l2cache.prefetcher.pfSpanPage 246425 # number of prefetches not generated due to page crossing
|
|
system.cpu0.l2cache.tags.replacements 273842 # number of replacements
|
|
system.cpu0.l2cache.tags.tagsinuse 16083.519419 # Cycle average of tags in use
|
|
system.cpu0.l2cache.tags.total_refs 3089138 # Total number of references to valid blocks.
|
|
system.cpu0.l2cache.tags.sampled_refs 289977 # Sample count of references to valid blocks.
|
|
system.cpu0.l2cache.tags.avg_refs 10.653045 # Average number of references to valid blocks.
|
|
system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.l2cache.tags.occ_blocks::writebacks 14593.575431 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.644607 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.130850 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1489.168531 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_percent::writebacks 0.890721 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000039 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.090892 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::total 0.981660 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1031 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 3 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15101 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 282 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 325 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 414 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3285 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7655 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3857 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062927 # Percentage of cache occupancy per task id
|
|
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000183 # Percentage of cache occupancy per task id
|
|
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.921692 # Percentage of cache occupancy per task id
|
|
system.cpu0.l2cache.tags.tag_accesses 63340451 # Number of tag accesses
|
|
system.cpu0.l2cache.tags.data_accesses 63340451 # Number of data accesses
|
|
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 11537 # number of ReadReq hits
|
|
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4979 # number of ReadReq hits
|
|
system.cpu0.l2cache.ReadReq_hits::total 16516 # number of ReadReq hits
|
|
system.cpu0.l2cache.WritebackDirty_hits::writebacks 507696 # number of WritebackDirty hits
|
|
system.cpu0.l2cache.WritebackDirty_hits::total 507696 # number of WritebackDirty hits
|
|
system.cpu0.l2cache.WritebackClean_hits::writebacks 1358751 # number of WritebackClean hits
|
|
system.cpu0.l2cache.WritebackClean_hits::total 1358751 # number of WritebackClean hits
|
|
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 241135 # number of ReadExReq hits
|
|
system.cpu0.l2cache.ReadExReq_hits::total 241135 # number of ReadExReq hits
|
|
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1108628 # number of ReadCleanReq hits
|
|
system.cpu0.l2cache.ReadCleanReq_hits::total 1108628 # number of ReadCleanReq hits
|
|
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 416937 # number of ReadSharedReq hits
|
|
system.cpu0.l2cache.ReadSharedReq_hits::total 416937 # number of ReadSharedReq hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 11537 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4979 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.inst 1108628 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.data 658072 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::total 1783216 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 11537 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4979 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.inst 1108628 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.data 658072 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::total 1783216 # number of overall hits
|
|
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 155 # number of ReadReq misses
|
|
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 97 # number of ReadReq misses
|
|
system.cpu0.l2cache.ReadReq_misses::total 252 # number of ReadReq misses
|
|
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55316 # number of UpgradeReq misses
|
|
system.cpu0.l2cache.UpgradeReq_misses::total 55316 # number of UpgradeReq misses
|
|
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19844 # number of SCUpgradeReq misses
|
|
system.cpu0.l2cache.SCUpgradeReq_misses::total 19844 # number of SCUpgradeReq misses
|
|
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses
|
|
system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses
|
|
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43803 # number of ReadExReq misses
|
|
system.cpu0.l2cache.ReadExReq_misses::total 43803 # number of ReadExReq misses
|
|
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 46498 # number of ReadCleanReq misses
|
|
system.cpu0.l2cache.ReadCleanReq_misses::total 46498 # number of ReadCleanReq misses
|
|
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 94557 # number of ReadSharedReq misses
|
|
system.cpu0.l2cache.ReadSharedReq_misses::total 94557 # number of ReadSharedReq misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 155 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 97 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.inst 46498 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.data 138360 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::total 185110 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 155 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 97 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.inst 46498 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.data 138360 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::total 185110 # number of overall misses
|
|
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 4266000 # number of ReadReq miss cycles
|
|
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2540500 # number of ReadReq miss cycles
|
|
system.cpu0.l2cache.ReadReq_miss_latency::total 6806500 # number of ReadReq miss cycles
|
|
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 172322000 # number of UpgradeReq miss cycles
|
|
system.cpu0.l2cache.UpgradeReq_miss_latency::total 172322000 # number of UpgradeReq miss cycles
|
|
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 43306000 # number of SCUpgradeReq miss cycles
|
|
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 43306000 # number of SCUpgradeReq miss cycles
|
|
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1349997 # number of SCUpgradeFailReq miss cycles
|
|
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1349997 # number of SCUpgradeFailReq miss cycles
|
|
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2802544000 # number of ReadExReq miss cycles
|
|
system.cpu0.l2cache.ReadExReq_miss_latency::total 2802544000 # number of ReadExReq miss cycles
|
|
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3338173500 # number of ReadCleanReq miss cycles
|
|
system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3338173500 # number of ReadCleanReq miss cycles
|
|
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3246573500 # number of ReadSharedReq miss cycles
|
|
system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3246573500 # number of ReadSharedReq miss cycles
|
|
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 4266000 # number of demand (read+write) miss cycles
|
|
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2540500 # number of demand (read+write) miss cycles
|
|
system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3338173500 # number of demand (read+write) miss cycles
|
|
system.cpu0.l2cache.demand_miss_latency::cpu0.data 6049117500 # number of demand (read+write) miss cycles
|
|
system.cpu0.l2cache.demand_miss_latency::total 9394097500 # number of demand (read+write) miss cycles
|
|
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 4266000 # number of overall miss cycles
|
|
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2540500 # number of overall miss cycles
|
|
system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3338173500 # number of overall miss cycles
|
|
system.cpu0.l2cache.overall_miss_latency::cpu0.data 6049117500 # number of overall miss cycles
|
|
system.cpu0.l2cache.overall_miss_latency::total 9394097500 # number of overall miss cycles
|
|
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 11692 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5076 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadReq_accesses::total 16768 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.l2cache.WritebackDirty_accesses::writebacks 507696 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu0.l2cache.WritebackDirty_accesses::total 507696 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu0.l2cache.WritebackClean_accesses::writebacks 1358751 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu0.l2cache.WritebackClean_accesses::total 1358751 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55316 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.UpgradeReq_accesses::total 55316 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19844 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.SCUpgradeReq_accesses::total 19844 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses)
|
|
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 284938 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadExReq_accesses::total 284938 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1155126 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadCleanReq_accesses::total 1155126 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 511494 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadSharedReq_accesses::total 511494 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 11692 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5076 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::cpu0.inst 1155126 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::cpu0.data 796432 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::total 1968326 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 11692 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5076 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.inst 1155126 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.data 796432 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::total 1968326 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.013257 # miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.019110 # miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.ReadReq_miss_rate::total 0.015029 # miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses
|
|
system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
|
|
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
|
|
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
|
|
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.153728 # miss rate for ReadExReq accesses
|
|
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.153728 # miss rate for ReadExReq accesses
|
|
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.040254 # miss rate for ReadCleanReq accesses
|
|
system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.040254 # miss rate for ReadCleanReq accesses
|
|
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.184864 # miss rate for ReadSharedReq accesses
|
|
system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.184864 # miss rate for ReadSharedReq accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.013257 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.019110 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040254 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.173725 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::total 0.094044 # miss rate for demand accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.013257 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.019110 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040254 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.173725 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::total 0.094044 # miss rate for overall accesses
|
|
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27522.580645 # average ReadReq miss latency
|
|
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 26190.721649 # average ReadReq miss latency
|
|
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27009.920635 # average ReadReq miss latency
|
|
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3115.228867 # average UpgradeReq miss latency
|
|
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3115.228867 # average UpgradeReq miss latency
|
|
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 2182.322112 # average SCUpgradeReq miss latency
|
|
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 2182.322112 # average SCUpgradeReq miss latency
|
|
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 269999.400000 # average SCUpgradeFailReq miss latency
|
|
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 269999.400000 # average SCUpgradeFailReq miss latency
|
|
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63980.640595 # average ReadExReq miss latency
|
|
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63980.640595 # average ReadExReq miss latency
|
|
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 71791.765237 # average ReadCleanReq miss latency
|
|
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 71791.765237 # average ReadCleanReq miss latency
|
|
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34334.565394 # average ReadSharedReq miss latency
|
|
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34334.565394 # average ReadSharedReq miss latency
|
|
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27522.580645 # average overall miss latency
|
|
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 26190.721649 # average overall miss latency
|
|
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 71791.765237 # average overall miss latency
|
|
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43720.132264 # average overall miss latency
|
|
system.cpu0.l2cache.demand_avg_miss_latency::total 50748.730485 # average overall miss latency
|
|
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27522.580645 # average overall miss latency
|
|
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 26190.721649 # average overall miss latency
|
|
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 71791.765237 # average overall miss latency
|
|
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43720.132264 # average overall miss latency
|
|
system.cpu0.l2cache.overall_avg_miss_latency::total 50748.730485 # average overall miss latency
|
|
system.cpu0.l2cache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked
|
|
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
|
|
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 32 # average number of cycles each access was blocked
|
|
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.l2cache.writebacks::writebacks 232272 # number of writebacks
|
|
system.cpu0.l2cache.writebacks::total 232272 # number of writebacks
|
|
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1851 # number of ReadExReq MSHR hits
|
|
system.cpu0.l2cache.ReadExReq_mshr_hits::total 1851 # number of ReadExReq MSHR hits
|
|
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 57 # number of ReadSharedReq MSHR hits
|
|
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 57 # number of ReadSharedReq MSHR hits
|
|
system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1908 # number of demand (read+write) MSHR hits
|
|
system.cpu0.l2cache.demand_mshr_hits::total 1908 # number of demand (read+write) MSHR hits
|
|
system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1908 # number of overall MSHR hits
|
|
system.cpu0.l2cache.overall_mshr_hits::total 1908 # number of overall MSHR hits
|
|
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 155 # number of ReadReq MSHR misses
|
|
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 97 # number of ReadReq MSHR misses
|
|
system.cpu0.l2cache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses
|
|
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 264558 # number of HardPFReq MSHR misses
|
|
system.cpu0.l2cache.HardPFReq_mshr_misses::total 264558 # number of HardPFReq MSHR misses
|
|
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55316 # number of UpgradeReq MSHR misses
|
|
system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55316 # number of UpgradeReq MSHR misses
|
|
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19844 # number of SCUpgradeReq MSHR misses
|
|
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19844 # number of SCUpgradeReq MSHR misses
|
|
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses
|
|
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses
|
|
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41952 # number of ReadExReq MSHR misses
|
|
system.cpu0.l2cache.ReadExReq_mshr_misses::total 41952 # number of ReadExReq MSHR misses
|
|
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 46498 # number of ReadCleanReq MSHR misses
|
|
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 46498 # number of ReadCleanReq MSHR misses
|
|
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 94500 # number of ReadSharedReq MSHR misses
|
|
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 94500 # number of ReadSharedReq MSHR misses
|
|
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 155 # number of demand (read+write) MSHR misses
|
|
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 97 # number of demand (read+write) MSHR misses
|
|
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 46498 # number of demand (read+write) MSHR misses
|
|
system.cpu0.l2cache.demand_mshr_misses::cpu0.data 136452 # number of demand (read+write) MSHR misses
|
|
system.cpu0.l2cache.demand_mshr_misses::total 183202 # number of demand (read+write) MSHR misses
|
|
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 155 # number of overall MSHR misses
|
|
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 97 # number of overall MSHR misses
|
|
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 46498 # number of overall MSHR misses
|
|
system.cpu0.l2cache.overall_mshr_misses::cpu0.data 136452 # number of overall MSHR misses
|
|
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 264558 # number of overall MSHR misses
|
|
system.cpu0.l2cache.overall_mshr_misses::total 447760 # number of overall MSHR misses
|
|
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31860 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40882 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28553 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28553 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
|
|
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60413 # number of overall MSHR uncacheable misses
|
|
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69435 # number of overall MSHR uncacheable misses
|
|
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3336000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1958500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 5294500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 20402670222 # number of HardPFReq MSHR miss cycles
|
|
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 20402670222 # number of HardPFReq MSHR miss cycles
|
|
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1434169000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1434169000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 342730000 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 342730000 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1097997 # number of SCUpgradeFailReq MSHR miss cycles
|
|
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1097997 # number of SCUpgradeFailReq MSHR miss cycles
|
|
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2366849000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2366849000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3059185500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3059185500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2673492000 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2673492000 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 3336000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1958500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3059185500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5040341000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.l2cache.demand_mshr_miss_latency::total 8104821000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3336000 # number of overall MSHR miss cycles
|
|
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1958500 # number of overall MSHR miss cycles
|
|
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3059185500 # number of overall MSHR miss cycles
|
|
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5040341000 # number of overall MSHR miss cycles
|
|
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 20402670222 # number of overall MSHR miss cycles
|
|
system.cpu0.l2cache.overall_mshr_miss_latency::total 28507491222 # number of overall MSHR miss cycles
|
|
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6386259500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7572471000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5200454500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5200454500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11586714000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12772925500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.013257 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.019110 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.015029 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
|
|
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
|
|
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.147232 # mshr miss rate for ReadExReq accesses
|
|
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.147232 # mshr miss rate for ReadExReq accesses
|
|
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.040254 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040254 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.184753 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.184753 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.013257 # mshr miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.019110 # mshr miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.040254 # mshr miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.171329 # mshr miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.093075 # mshr miss rate for demand accesses
|
|
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.013257 # mshr miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.019110 # mshr miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.040254 # mshr miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.171329 # mshr miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.227483 # mshr miss rate for overall accesses
|
|
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21522.580645 # average ReadReq mshr miss latency
|
|
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 20190.721649 # average ReadReq mshr miss latency
|
|
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21009.920635 # average ReadReq mshr miss latency
|
|
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 77119.838455 # average HardPFReq mshr miss latency
|
|
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 77119.838455 # average HardPFReq mshr miss latency
|
|
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25926.838528 # average UpgradeReq mshr miss latency
|
|
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25926.838528 # average UpgradeReq mshr miss latency
|
|
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17271.215481 # average SCUpgradeReq mshr miss latency
|
|
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17271.215481 # average SCUpgradeReq mshr miss latency
|
|
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 219599.400000 # average SCUpgradeFailReq mshr miss latency
|
|
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 219599.400000 # average SCUpgradeFailReq mshr miss latency
|
|
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56418.025362 # average ReadExReq mshr miss latency
|
|
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56418.025362 # average ReadExReq mshr miss latency
|
|
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 65791.765237 # average ReadCleanReq mshr miss latency
|
|
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65791.765237 # average ReadCleanReq mshr miss latency
|
|
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28290.920635 # average ReadSharedReq mshr miss latency
|
|
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28290.920635 # average ReadSharedReq mshr miss latency
|
|
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21522.580645 # average overall mshr miss latency
|
|
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20190.721649 # average overall mshr miss latency
|
|
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 65791.765237 # average overall mshr miss latency
|
|
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36938.564477 # average overall mshr miss latency
|
|
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44239.806334 # average overall mshr miss latency
|
|
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21522.580645 # average overall mshr miss latency
|
|
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20190.721649 # average overall mshr miss latency
|
|
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 65791.765237 # average overall mshr miss latency
|
|
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36938.564477 # average overall mshr miss latency
|
|
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 77119.838455 # average overall mshr miss latency
|
|
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63666.900174 # average overall mshr miss latency
|
|
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200447.567483 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185227.508439 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182133.383532 # average WriteReq mshr uncacheable latency
|
|
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182133.383532 # average WriteReq mshr uncacheable latency
|
|
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average overall mshr uncacheable latency
|
|
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191791.733567 # average overall mshr uncacheable latency
|
|
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183955.145100 # average overall mshr uncacheable latency
|
|
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.toL2Bus.snoop_filter.tot_requests 3935499 # Total number of requests made to the snoop filter.
|
|
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1983981 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 29039 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu0.toL2Bus.snoop_filter.tot_snoops 320941 # Total number of snoops made to the snoop filter.
|
|
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 317478 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3463 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu0.toL2Bus.trans_dist::ReadReq 63971 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadResp 1779248 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::WriteReq 28553 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::WriteResp 28553 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::WritebackDirty 740475 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::WritebackClean 1358751 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::CleanEvict 190136 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::HardPFReq 311790 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::UpgradeReq 85728 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41989 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::UpgradeResp 112642 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 35 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadExReq 304006 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadExResp 300714 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1155126 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 580591 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::InvalidateReq 3227 # Transaction distribution
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3461069 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2699694 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12104 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 27735 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count::total 6200602 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 146461624 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 102248167 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 20304 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 46768 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size::total 248776863 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.snoops 987005 # Total snoops (count)
|
|
system.cpu0.toL2Bus.snoop_fanout::samples 2997932 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::mean 0.122336 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::stdev 0.331180 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::0 2634639 87.88% 87.88% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::1 359830 12.00% 99.88% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::2 3463 0.12% 100.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::total 2997932 # Request fanout histogram
|
|
system.cpu0.toL2Bus.reqLayer0.occupancy 3917122496 # Layer occupancy (ticks)
|
|
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu0.toL2Bus.snoopLayer0.occupancy 115533329 # Layer occupancy (ticks)
|
|
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu0.toL2Bus.respLayer0.occupancy 1741711000 # Layer occupancy (ticks)
|
|
system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu0.toL2Bus.respLayer1.occupancy 1278424980 # Layer occupancy (ticks)
|
|
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.cpu0.toL2Bus.respLayer2.occupancy 7028000 # Layer occupancy (ticks)
|
|
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.cpu0.toL2Bus.respLayer3.occupancy 16050485 # Layer occupancy (ticks)
|
|
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.dtb.walker.walks 2352 # Table walker walks requested
|
|
system.cpu1.dtb.walker.walksShort 2352 # Table walker walks initiated with short descriptors
|
|
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 487 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1865 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu1.dtb.walker.walkWaitTime::samples 2352 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::0 2352 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::total 2352 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::samples 1706 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::mean 11672.919109 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::gmean 11010.748339 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::stdev 5645.878722 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::0-16383 1558 91.32% 91.32% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::16384-32767 139 8.15% 99.47% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::32768-49151 5 0.29% 99.77% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.18% 99.94% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.06% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::total 1706 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walksPending::samples -1207257828 # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::0 -1207257828 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::total -1207257828 # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walkPageSizes::4K 1219 71.45% 71.45% # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkPageSizes::1M 487 28.55% 100.00% # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkPageSizes::total 1706 # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2352 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2352 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1706 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1706 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin::total 4058 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 3283088 # DTB read hits
|
|
system.cpu1.dtb.read_misses 1969 # DTB read misses
|
|
system.cpu1.dtb.write_hits 2849660 # DTB write hits
|
|
system.cpu1.dtb.write_misses 383 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 1653 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 218 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 124 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 3285057 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 2850043 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 6132748 # DTB hits
|
|
system.cpu1.dtb.misses 2352 # DTB misses
|
|
system.cpu1.dtb.accesses 6135100 # DTB accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.itb.walker.walks 1376 # Table walker walks requested
|
|
system.cpu1.itb.walker.walksShort 1376 # Table walker walks initiated with short descriptors
|
|
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 134 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1242 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu1.itb.walker.walkWaitTime::samples 1376 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkWaitTime::0 1376 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkWaitTime::total 1376 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::samples 819 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::mean 11896.825397 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::gmean 11258.920739 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::stdev 5216.232861 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::4096-8191 112 13.68% 13.68% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::8192-12287 592 72.28% 85.96% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::12288-16383 66 8.06% 94.02% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::16384-20479 7 0.85% 94.87% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.24% 95.12% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::24576-28671 24 2.93% 98.05% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::28672-32767 5 0.61% 98.66% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 98.78% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::36864-40959 6 0.73% 99.51% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.24% 99.76% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.12% 99.88% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.12% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::total 819 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walksPending::samples -1208095828 # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walksPending::0 -1208095828 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walksPending::total -1208095828 # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walkPageSizes::4K 685 83.64% 83.64% # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkPageSizes::1M 134 16.36% 100.00% # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkPageSizes::total 819 # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1376 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1376 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 819 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 819 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin::total 2195 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.inst_hits 13713445 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 1376 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 883 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 13714821 # ITB inst accesses
|
|
system.cpu1.itb.hits 13713445 # DTB hits
|
|
system.cpu1.itb.misses 1376 # DTB misses
|
|
system.cpu1.itb.accesses 13714821 # DTB accesses
|
|
system.cpu1.numCycles 5742759797 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 2753 # number of quiesce instructions executed
|
|
system.cpu1.committedInsts 13517417 # Number of instructions committed
|
|
system.cpu1.committedOps 16437338 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 14911378 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 901174 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 1468136 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 14911378 # number of integer instructions
|
|
system.cpu1.num_fp_insts 0 # number of float instructions
|
|
system.cpu1.num_int_register_reads 27063131 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 10536793 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
|
|
system.cpu1.num_cc_register_reads 60344215 # number of times the CC registers were read
|
|
system.cpu1.num_cc_register_writes 5099594 # number of times the CC registers were written
|
|
system.cpu1.num_mem_refs 6349896 # number of memory refs
|
|
system.cpu1.num_load_insts 3389045 # Number of load instructions
|
|
system.cpu1.num_store_insts 2960851 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 5696813538.222876 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 45946258.777124 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.008001 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.991999 # Percentage of idle cycles
|
|
system.cpu1.Branches 2418797 # Number of branches fetched
|
|
system.cpu1.op_class::No_OpClass 24 0.00% 0.00% # Class of executed instruction
|
|
system.cpu1.op_class::IntAlu 10377527 61.94% 61.94% # Class of executed instruction
|
|
system.cpu1.op_class::IntMult 24492 0.15% 62.08% # Class of executed instruction
|
|
system.cpu1.op_class::IntDiv 0 0.00% 62.08% # Class of executed instruction
|
|
system.cpu1.op_class::FloatAdd 0 0.00% 62.08% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCmp 0 0.00% 62.08% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCvt 0 0.00% 62.08% # Class of executed instruction
|
|
system.cpu1.op_class::FloatMult 0 0.00% 62.08% # Class of executed instruction
|
|
system.cpu1.op_class::FloatDiv 0 0.00% 62.08% # Class of executed instruction
|
|
system.cpu1.op_class::FloatSqrt 0 0.00% 62.08% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAdd 0 0.00% 62.08% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAddAcc 0 0.00% 62.08% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAlu 0 0.00% 62.08% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCmp 0 0.00% 62.08% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCvt 0 0.00% 62.08% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMisc 0 0.00% 62.08% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMult 0 0.00% 62.08% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMultAcc 0 0.00% 62.08% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShift 0 0.00% 62.08% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.08% # Class of executed instruction
|
|
system.cpu1.op_class::SimdSqrt 0 0.00% 62.08% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.08% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.08% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.08% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.08% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.08% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMisc 3134 0.02% 62.10% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMult 0 0.00% 62.10% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.10% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.10% # Class of executed instruction
|
|
system.cpu1.op_class::MemRead 3389045 20.23% 82.33% # Class of executed instruction
|
|
system.cpu1.op_class::MemWrite 2960851 17.67% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::total 16755073 # Class of executed instruction
|
|
system.cpu1.dcache.tags.replacements 144073 # number of replacements
|
|
system.cpu1.dcache.tags.tagsinuse 473.219627 # Cycle average of tags in use
|
|
system.cpu1.dcache.tags.total_refs 5912733 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.tags.sampled_refs 144418 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.tags.avg_refs 40.941801 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.tags.warmup_cycle 106295131000 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.tags.occ_blocks::cpu1.data 473.219627 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.924257 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_percent::total 0.924257 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_task_id_blocks::1024 345 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 26 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.673828 # Percentage of cache occupancy per task id
|
|
system.cpu1.dcache.tags.tag_accesses 12441829 # Number of tag accesses
|
|
system.cpu1.dcache.tags.data_accesses 12441829 # Number of data accesses
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 3018165 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 3018165 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 2685196 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 2685196 # number of WriteReq hits
|
|
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 41245 # number of SoftPFReq hits
|
|
system.cpu1.dcache.SoftPFReq_hits::total 41245 # number of SoftPFReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 69563 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::total 69563 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61182 # number of StoreCondReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::total 61182 # number of StoreCondReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 5703361 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 5703361 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 5744606 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 5744606 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 110713 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 110713 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 77621 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 77621 # number of WriteReq misses
|
|
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 23905 # number of SoftPFReq misses
|
|
system.cpu1.dcache.SoftPFReq_misses::total 23905 # number of SoftPFReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16417 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::total 16417 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23076 # number of StoreCondReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::total 23076 # number of StoreCondReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 188334 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 188334 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 212239 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 212239 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1730591500 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_latency::total 1730591500 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2713528000 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::total 2713528000 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 316809000 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::total 316809000 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 632764000 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::total 632764000 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3307000 # number of StoreCondFailReq miss cycles
|
|
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3307000 # number of StoreCondFailReq miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::cpu1.data 4444119500 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::total 4444119500 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::cpu1.data 4444119500 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::total 4444119500 # number of overall miss cycles
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 3128878 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 3128878 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 2762817 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 2762817 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 65150 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu1.dcache.SoftPFReq_accesses::total 65150 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 85980 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::total 85980 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 84258 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::total 84258 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 5891695 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 5891695 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 5956845 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 5956845 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035384 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.035384 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028095 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.028095 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.366922 # miss rate for SoftPFReq accesses
|
|
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.366922 # miss rate for SoftPFReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.190940 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.190940 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.273873 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.273873 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031966 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.031966 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035629 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.035629 # miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15631.330557 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15631.330557 # average ReadReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34958.683861 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total 34958.683861 # average WriteReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19297.618322 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19297.618322 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27420.870168 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27420.870168 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
|
|
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23597.011161 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::total 23597.011161 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20939.221821 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::total 20939.221821 # average overall miss latency
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.writebacks::writebacks 144073 # number of writebacks
|
|
system.cpu1.dcache.writebacks::total 144073 # number of writebacks
|
|
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 168 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_hits::total 168 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11530 # number of LoadLockedReq MSHR hits
|
|
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11530 # number of LoadLockedReq MSHR hits
|
|
system.cpu1.dcache.demand_mshr_hits::cpu1.data 168 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.demand_mshr_hits::total 168 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.overall_mshr_hits::cpu1.data 168 # number of overall MSHR hits
|
|
system.cpu1.dcache.overall_mshr_hits::total 168 # number of overall MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 110545 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_misses::total 110545 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 77621 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::total 77621 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23508 # number of SoftPFReq MSHR misses
|
|
system.cpu1.dcache.SoftPFReq_mshr_misses::total 23508 # number of SoftPFReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4887 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4887 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23076 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::total 23076 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::cpu1.data 188166 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::total 188166 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 211674 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::total 211674 # number of overall MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3107 # number of ReadReq MSHR uncacheable
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3107 # number of ReadReq MSHR uncacheable
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2430 # number of WriteReq MSHR uncacheable
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2430 # number of WriteReq MSHR uncacheable
|
|
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5537 # number of overall MSHR uncacheable misses
|
|
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5537 # number of overall MSHR uncacheable misses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1611627000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1611627000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2635907000 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2635907000 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 421753500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 421753500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88480500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88480500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 609718000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 609718000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3277000 # number of StoreCondFailReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3277000 # number of StoreCondFailReq MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4247534000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::total 4247534000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4669287500 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::total 4669287500 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 430617000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 430617000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 292641500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 292641500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 723258500 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 723258500 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035331 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035331 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028095 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028095 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.360829 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.360829 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056839 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056839 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.273873 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.273873 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031937 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total 0.031937 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035535 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total 0.035535 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14578.922611 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14578.922611 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33958.683861 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33958.683861 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17940.849923 # average SoftPFReq mshr miss latency
|
|
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17940.849923 # average SoftPFReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18105.279312 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18105.279312 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26422.170220 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26422.170220 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22573.334184 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22573.334184 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22058.861740 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22058.861740 # average overall mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 138595.751529 # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 138595.751529 # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 120428.600823 # average WriteReq mshr uncacheable latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 120428.600823 # average WriteReq mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 130622.810186 # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 130622.810186 # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.icache.tags.replacements 461792 # number of replacements
|
|
system.cpu1.icache.tags.tagsinuse 498.311266 # Cycle average of tags in use
|
|
system.cpu1.icache.tags.total_refs 13251136 # Total number of references to valid blocks.
|
|
system.cpu1.icache.tags.sampled_refs 462304 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.tags.avg_refs 28.663252 # Average number of references to valid blocks.
|
|
system.cpu1.icache.tags.warmup_cycle 106195905000 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.311266 # Average occupied blocks per requestor
|
|
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973264 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_percent::total 0.973264 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::3 118 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu1.icache.tags.tag_accesses 27889184 # Number of tag accesses
|
|
system.cpu1.icache.tags.data_accesses 27889184 # Number of data accesses
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 13251136 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 13251136 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 13251136 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 13251136 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 13251136 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 13251136 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 462304 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 462304 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 462304 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 462304 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 462304 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 462304 # number of overall misses
|
|
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4149723500 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_latency::total 4149723500 # number of ReadReq miss cycles
|
|
system.cpu1.icache.demand_miss_latency::cpu1.inst 4149723500 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_latency::total 4149723500 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.overall_miss_latency::cpu1.inst 4149723500 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_latency::total 4149723500 # number of overall miss cycles
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 13713440 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 13713440 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 13713440 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 13713440 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 13713440 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 13713440 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033712 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.033712 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033712 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.033712 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033712 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.033712 # miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8976.179094 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total 8976.179094 # average ReadReq miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8976.179094 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::total 8976.179094 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8976.179094 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::total 8976.179094 # average overall miss latency
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.writebacks::writebacks 461792 # number of writebacks
|
|
system.cpu1.icache.writebacks::total 461792 # number of writebacks
|
|
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 462304 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_misses::total 462304 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::cpu1.inst 462304 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::total 462304 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::cpu1.inst 462304 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::total 462304 # number of overall MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable
|
|
system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable
|
|
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses
|
|
system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3918571500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::total 3918571500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3918571500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::total 3918571500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3918571500 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::total 3918571500 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 23546500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 23546500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 23546500 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency::total 23546500 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.033712 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.033712 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.033712 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::total 0.033712 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.033712 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::total 0.033712 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8476.179094 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8476.179094 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8476.179094 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::total 8476.179094 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8476.179094 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::total 8476.179094 # average overall mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average ReadReq mshr uncacheable latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133031.073446 # average ReadReq mshr uncacheable latency
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average overall mshr uncacheable latency
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133031.073446 # average overall mshr uncacheable latency
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.l2cache.prefetcher.num_hwpf_issued 106104 # number of hwpf issued
|
|
system.cpu1.l2cache.prefetcher.pfIdentified 106112 # number of prefetch candidates identified
|
|
system.cpu1.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue
|
|
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
|
|
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
|
|
system.cpu1.l2cache.prefetcher.pfSpanPage 50448 # number of prefetches not generated due to page crossing
|
|
system.cpu1.l2cache.tags.replacements 30131 # number of replacements
|
|
system.cpu1.l2cache.tags.tagsinuse 14949.290291 # Cycle average of tags in use
|
|
system.cpu1.l2cache.tags.total_refs 1034569 # Total number of references to valid blocks.
|
|
system.cpu1.l2cache.tags.sampled_refs 45193 # Sample count of references to valid blocks.
|
|
system.cpu1.l2cache.tags.avg_refs 22.892240 # Average number of references to valid blocks.
|
|
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.l2cache.tags.occ_blocks::writebacks 14514.476865 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.312401 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.041451 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 430.459574 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_percent::writebacks 0.885893 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000141 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000125 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.026273 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::total 0.912432 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 971 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 32 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14059 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 54 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 913 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 27 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 390 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1365 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 12304 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.059265 # Percentage of cache occupancy per task id
|
|
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001953 # Percentage of cache occupancy per task id
|
|
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.858093 # Percentage of cache occupancy per task id
|
|
system.cpu1.l2cache.tags.tag_accesses 20957142 # Number of tag accesses
|
|
system.cpu1.l2cache.tags.data_accesses 20957142 # Number of data accesses
|
|
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 2443 # number of ReadReq hits
|
|
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1453 # number of ReadReq hits
|
|
system.cpu1.l2cache.ReadReq_hits::total 3896 # number of ReadReq hits
|
|
system.cpu1.l2cache.WritebackDirty_hits::writebacks 89055 # number of WritebackDirty hits
|
|
system.cpu1.l2cache.WritebackDirty_hits::total 89055 # number of WritebackDirty hits
|
|
system.cpu1.l2cache.WritebackClean_hits::writebacks 506752 # number of WritebackClean hits
|
|
system.cpu1.l2cache.WritebackClean_hits::total 506752 # number of WritebackClean hits
|
|
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 16650 # number of ReadExReq hits
|
|
system.cpu1.l2cache.ReadExReq_hits::total 16650 # number of ReadExReq hits
|
|
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 453968 # number of ReadCleanReq hits
|
|
system.cpu1.l2cache.ReadCleanReq_hits::total 453968 # number of ReadCleanReq hits
|
|
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 75407 # number of ReadSharedReq hits
|
|
system.cpu1.l2cache.ReadSharedReq_hits::total 75407 # number of ReadSharedReq hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 2443 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1453 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.inst 453968 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.data 92057 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::total 549921 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 2443 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1453 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.inst 453968 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.data 92057 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::total 549921 # number of overall hits
|
|
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 349 # number of ReadReq misses
|
|
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 301 # number of ReadReq misses
|
|
system.cpu1.l2cache.ReadReq_misses::total 650 # number of ReadReq misses
|
|
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28928 # number of UpgradeReq misses
|
|
system.cpu1.l2cache.UpgradeReq_misses::total 28928 # number of UpgradeReq misses
|
|
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23076 # number of SCUpgradeReq misses
|
|
system.cpu1.l2cache.SCUpgradeReq_misses::total 23076 # number of SCUpgradeReq misses
|
|
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32043 # number of ReadExReq misses
|
|
system.cpu1.l2cache.ReadExReq_misses::total 32043 # number of ReadExReq misses
|
|
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 8336 # number of ReadCleanReq misses
|
|
system.cpu1.l2cache.ReadCleanReq_misses::total 8336 # number of ReadCleanReq misses
|
|
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 63533 # number of ReadSharedReq misses
|
|
system.cpu1.l2cache.ReadSharedReq_misses::total 63533 # number of ReadSharedReq misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 349 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 301 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.inst 8336 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.data 95576 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::total 104562 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 349 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 301 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.inst 8336 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.data 95576 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::total 104562 # number of overall misses
|
|
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 7078500 # number of ReadReq miss cycles
|
|
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6021500 # number of ReadReq miss cycles
|
|
system.cpu1.l2cache.ReadReq_miss_latency::total 13100000 # number of ReadReq miss cycles
|
|
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 62132500 # number of UpgradeReq miss cycles
|
|
system.cpu1.l2cache.UpgradeReq_miss_latency::total 62132500 # number of UpgradeReq miss cycles
|
|
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 59033500 # number of SCUpgradeReq miss cycles
|
|
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 59033500 # number of SCUpgradeReq miss cycles
|
|
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3231500 # number of SCUpgradeFailReq miss cycles
|
|
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3231500 # number of SCUpgradeFailReq miss cycles
|
|
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1646554500 # number of ReadExReq miss cycles
|
|
system.cpu1.l2cache.ReadExReq_miss_latency::total 1646554500 # number of ReadExReq miss cycles
|
|
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 475139500 # number of ReadCleanReq miss cycles
|
|
system.cpu1.l2cache.ReadCleanReq_miss_latency::total 475139500 # number of ReadCleanReq miss cycles
|
|
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1418811000 # number of ReadSharedReq miss cycles
|
|
system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1418811000 # number of ReadSharedReq miss cycles
|
|
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 7078500 # number of demand (read+write) miss cycles
|
|
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6021500 # number of demand (read+write) miss cycles
|
|
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 475139500 # number of demand (read+write) miss cycles
|
|
system.cpu1.l2cache.demand_miss_latency::cpu1.data 3065365500 # number of demand (read+write) miss cycles
|
|
system.cpu1.l2cache.demand_miss_latency::total 3553605000 # number of demand (read+write) miss cycles
|
|
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 7078500 # number of overall miss cycles
|
|
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6021500 # number of overall miss cycles
|
|
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 475139500 # number of overall miss cycles
|
|
system.cpu1.l2cache.overall_miss_latency::cpu1.data 3065365500 # number of overall miss cycles
|
|
system.cpu1.l2cache.overall_miss_latency::total 3553605000 # number of overall miss cycles
|
|
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 2792 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1754 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadReq_accesses::total 4546 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l2cache.WritebackDirty_accesses::writebacks 89055 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu1.l2cache.WritebackDirty_accesses::total 89055 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu1.l2cache.WritebackClean_accesses::writebacks 506752 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu1.l2cache.WritebackClean_accesses::total 506752 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28928 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.UpgradeReq_accesses::total 28928 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23076 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.SCUpgradeReq_accesses::total 23076 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 48693 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadExReq_accesses::total 48693 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 462304 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadCleanReq_accesses::total 462304 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 138940 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadSharedReq_accesses::total 138940 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 2792 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1754 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::cpu1.inst 462304 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::cpu1.data 187633 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::total 654483 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 2792 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1754 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.inst 462304 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.data 187633 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::total 654483 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.171608 # miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.ReadReq_miss_rate::total 0.142983 # miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
|
|
system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
|
|
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.658062 # miss rate for ReadExReq accesses
|
|
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.658062 # miss rate for ReadExReq accesses
|
|
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.018031 # miss rate for ReadCleanReq accesses
|
|
system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.018031 # miss rate for ReadCleanReq accesses
|
|
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.457269 # miss rate for ReadSharedReq accesses
|
|
system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.457269 # miss rate for ReadSharedReq accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.171608 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.018031 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.509377 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::total 0.159763 # miss rate for demand accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.171608 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.018031 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.509377 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::total 0.159763 # miss rate for overall accesses
|
|
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20282.234957 # average ReadReq miss latency
|
|
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20004.983389 # average ReadReq miss latency
|
|
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20153.846154 # average ReadReq miss latency
|
|
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2147.832550 # average UpgradeReq miss latency
|
|
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2147.832550 # average UpgradeReq miss latency
|
|
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 2558.220662 # average SCUpgradeReq miss latency
|
|
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 2558.220662 # average SCUpgradeReq miss latency
|
|
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency
|
|
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
|
|
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 51385.778485 # average ReadExReq miss latency
|
|
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 51385.778485 # average ReadExReq miss latency
|
|
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 56998.500480 # average ReadCleanReq miss latency
|
|
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 56998.500480 # average ReadCleanReq miss latency
|
|
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22331.874774 # average ReadSharedReq miss latency
|
|
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22331.874774 # average ReadSharedReq miss latency
|
|
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20282.234957 # average overall miss latency
|
|
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20004.983389 # average overall miss latency
|
|
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 56998.500480 # average overall miss latency
|
|
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32072.544363 # average overall miss latency
|
|
system.cpu1.l2cache.demand_avg_miss_latency::total 33985.625753 # average overall miss latency
|
|
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20282.234957 # average overall miss latency
|
|
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20004.983389 # average overall miss latency
|
|
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 56998.500480 # average overall miss latency
|
|
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32072.544363 # average overall miss latency
|
|
system.cpu1.l2cache.overall_avg_miss_latency::total 33985.625753 # average overall miss latency
|
|
system.cpu1.l2cache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked
|
|
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
|
|
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 32 # average number of cycles each access was blocked
|
|
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.l2cache.writebacks::writebacks 25259 # number of writebacks
|
|
system.cpu1.l2cache.writebacks::total 25259 # number of writebacks
|
|
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 80 # number of ReadExReq MSHR hits
|
|
system.cpu1.l2cache.ReadExReq_mshr_hits::total 80 # number of ReadExReq MSHR hits
|
|
system.cpu1.l2cache.demand_mshr_hits::cpu1.data 80 # number of demand (read+write) MSHR hits
|
|
system.cpu1.l2cache.demand_mshr_hits::total 80 # number of demand (read+write) MSHR hits
|
|
system.cpu1.l2cache.overall_mshr_hits::cpu1.data 80 # number of overall MSHR hits
|
|
system.cpu1.l2cache.overall_mshr_hits::total 80 # number of overall MSHR hits
|
|
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 349 # number of ReadReq MSHR misses
|
|
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 301 # number of ReadReq MSHR misses
|
|
system.cpu1.l2cache.ReadReq_mshr_misses::total 650 # number of ReadReq MSHR misses
|
|
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 18771 # number of HardPFReq MSHR misses
|
|
system.cpu1.l2cache.HardPFReq_mshr_misses::total 18771 # number of HardPFReq MSHR misses
|
|
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28928 # number of UpgradeReq MSHR misses
|
|
system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28928 # number of UpgradeReq MSHR misses
|
|
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23076 # number of SCUpgradeReq MSHR misses
|
|
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23076 # number of SCUpgradeReq MSHR misses
|
|
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 31963 # number of ReadExReq MSHR misses
|
|
system.cpu1.l2cache.ReadExReq_mshr_misses::total 31963 # number of ReadExReq MSHR misses
|
|
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 8336 # number of ReadCleanReq MSHR misses
|
|
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 8336 # number of ReadCleanReq MSHR misses
|
|
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 63533 # number of ReadSharedReq MSHR misses
|
|
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 63533 # number of ReadSharedReq MSHR misses
|
|
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 349 # number of demand (read+write) MSHR misses
|
|
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 301 # number of demand (read+write) MSHR misses
|
|
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 8336 # number of demand (read+write) MSHR misses
|
|
system.cpu1.l2cache.demand_mshr_misses::cpu1.data 95496 # number of demand (read+write) MSHR misses
|
|
system.cpu1.l2cache.demand_mshr_misses::total 104482 # number of demand (read+write) MSHR misses
|
|
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 349 # number of overall MSHR misses
|
|
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 301 # number of overall MSHR misses
|
|
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 8336 # number of overall MSHR misses
|
|
system.cpu1.l2cache.overall_mshr_misses::cpu1.data 95496 # number of overall MSHR misses
|
|
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 18771 # number of overall MSHR misses
|
|
system.cpu1.l2cache.overall_mshr_misses::total 123253 # number of overall MSHR misses
|
|
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable
|
|
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3107 # number of ReadReq MSHR uncacheable
|
|
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3284 # number of ReadReq MSHR uncacheable
|
|
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2430 # number of WriteReq MSHR uncacheable
|
|
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2430 # number of WriteReq MSHR uncacheable
|
|
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses
|
|
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5537 # number of overall MSHR uncacheable misses
|
|
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5714 # number of overall MSHR uncacheable misses
|
|
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4984500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4215500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 9200000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 917123117 # number of HardPFReq MSHR miss cycles
|
|
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 917123117 # number of HardPFReq MSHR miss cycles
|
|
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 588451500 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 588451500 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 436537000 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 436537000 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3051500 # number of SCUpgradeFailReq MSHR miss cycles
|
|
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3051500 # number of SCUpgradeFailReq MSHR miss cycles
|
|
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1446140000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1446140000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 425123500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 425123500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1037613000 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1037613000 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4984500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4215500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 425123500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2483753000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.l2cache.demand_mshr_miss_latency::total 2918076500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4984500 # number of overall MSHR miss cycles
|
|
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4215500 # number of overall MSHR miss cycles
|
|
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 425123500 # number of overall MSHR miss cycles
|
|
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2483753000 # number of overall MSHR miss cycles
|
|
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 917123117 # number of overall MSHR miss cycles
|
|
system.cpu1.l2cache.overall_mshr_miss_latency::total 3835199617 # number of overall MSHR miss cycles
|
|
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 22219000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 405408000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 427627000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 274409000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 274409000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 22219000 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 679817000 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 702036000 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.171608 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.142983 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.656419 # mshr miss rate for ReadExReq accesses
|
|
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.656419 # mshr miss rate for ReadExReq accesses
|
|
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.018031 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.018031 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.457269 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.457269 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.171608 # mshr miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.018031 # mshr miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.508951 # mshr miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159641 # mshr miss rate for demand accesses
|
|
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.171608 # mshr miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.018031 # mshr miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.508951 # mshr miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.188321 # mshr miss rate for overall accesses
|
|
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14282.234957 # average ReadReq mshr miss latency
|
|
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14004.983389 # average ReadReq mshr miss latency
|
|
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14153.846154 # average ReadReq mshr miss latency
|
|
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48858.511374 # average HardPFReq mshr miss latency
|
|
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 48858.511374 # average HardPFReq mshr miss latency
|
|
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20341.935149 # average UpgradeReq mshr miss latency
|
|
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20341.935149 # average UpgradeReq mshr miss latency
|
|
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18917.360028 # average SCUpgradeReq mshr miss latency
|
|
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18917.360028 # average SCUpgradeReq mshr miss latency
|
|
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency
|
|
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
|
|
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45244.188593 # average ReadExReq mshr miss latency
|
|
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45244.188593 # average ReadExReq mshr miss latency
|
|
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 50998.500480 # average ReadCleanReq mshr miss latency
|
|
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50998.500480 # average ReadCleanReq mshr miss latency
|
|
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16331.874774 # average ReadSharedReq mshr miss latency
|
|
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16331.874774 # average ReadSharedReq mshr miss latency
|
|
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14282.234957 # average overall mshr miss latency
|
|
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14004.983389 # average overall mshr miss latency
|
|
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 50998.500480 # average overall mshr miss latency
|
|
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26008.974198 # average overall mshr miss latency
|
|
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27928.987768 # average overall mshr miss latency
|
|
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14282.234957 # average overall mshr miss latency
|
|
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14004.983389 # average overall mshr miss latency
|
|
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 50998.500480 # average overall mshr miss latency
|
|
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26008.974198 # average overall mshr miss latency
|
|
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48858.511374 # average overall mshr miss latency
|
|
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31116.480873 # average overall mshr miss latency
|
|
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average ReadReq mshr uncacheable latency
|
|
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 130482.137110 # average ReadReq mshr uncacheable latency
|
|
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 130215.286236 # average ReadReq mshr uncacheable latency
|
|
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 112925.514403 # average WriteReq mshr uncacheable latency
|
|
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 112925.514403 # average WriteReq mshr uncacheable latency
|
|
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average overall mshr uncacheable latency
|
|
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 122777.135633 # average overall mshr uncacheable latency
|
|
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 122862.443122 # average overall mshr uncacheable latency
|
|
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.toL2Bus.snoop_filter.tot_requests 1312846 # Total number of requests made to the snoop filter.
|
|
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 662941 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 10057 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu1.toL2Bus.snoop_filter.tot_snoops 166384 # Total number of snoops made to the snoop filter.
|
|
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164278 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2106 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu1.toL2Bus.trans_dist::ReadReq 10119 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadResp 648543 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::WriteReq 2430 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::WriteResp 2430 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::WritebackDirty 115438 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::WritebackClean 506752 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::CleanEvict 85166 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::HardPFReq 22864 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::UpgradeReq 70245 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40855 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::UpgradeResp 84598 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 42 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadExReq 55915 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadExResp 53326 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 462304 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 211564 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::InvalidateReq 31 # Transaction distribution
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1378500 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707096 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 4372 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 7009 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count::total 2096977 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 58614596 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 23813135 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7016 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 11168 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size::total 82445915 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.snoops 350196 # Total snoops (count)
|
|
system.cpu1.toL2Bus.snoop_fanout::samples 987919 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::mean 0.185835 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::stdev 0.394416 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::0 806435 81.63% 81.63% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::1 179378 18.16% 99.79% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::2 2106 0.21% 100.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::total 987919 # Request fanout histogram
|
|
system.cpu1.toL2Bus.reqLayer0.occupancy 1267256999 # Layer occupancy (ticks)
|
|
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu1.toL2Bus.snoopLayer0.occupancy 79126203 # Layer occupancy (ticks)
|
|
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu1.toL2Bus.respLayer0.occupancy 693633000 # Layer occupancy (ticks)
|
|
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu1.toL2Bus.respLayer1.occupancy 311803500 # Layer occupancy (ticks)
|
|
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.cpu1.toL2Bus.respLayer2.occupancy 2618000 # Layer occupancy (ticks)
|
|
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.cpu1.toL2Bus.respLayer3.occupancy 4217000 # Layer occupancy (ticks)
|
|
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.trans_dist::ReadReq 31009 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 31009 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 59425 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 59425 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56620 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 107934 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 180868 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71564 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 162814 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 2483990 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 48738000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 322000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 32500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer7.occupancy 93500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer8.occupancy 610000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 23500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 6150500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 32045500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 186301036 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 84733000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 36433 # number of replacements
|
|
system.iocache.tags.tagsinuse 1.018273 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 36449 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 290654223000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::realview.ide 1.018273 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::realview.ide 0.063642 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.063642 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 328203 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 328203 # Number of data accesses
|
|
system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 243 # number of ReadReq misses
|
|
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
|
|
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
|
|
system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 243 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::realview.ide 243 # number of overall misses
|
|
system.iocache.overall_misses::total 243 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::realview.ide 31405376 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 31405376 # number of ReadReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::realview.ide 4738596660 # number of WriteLineReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::total 4738596660 # number of WriteLineReq miss cycles
|
|
system.iocache.demand_miss_latency::realview.ide 31405376 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 31405376 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::realview.ide 31405376 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 31405376 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::realview.ide 129240.230453 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 129240.230453 # average ReadReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130813.732884 # average WriteLineReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::total 130813.732884 # average WriteLineReq miss latency
|
|
system.iocache.demand_avg_miss_latency::realview.ide 129240.230453 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 129240.230453 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::realview.ide 129240.230453 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 129240.230453 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 816 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 79 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 10.329114 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 36190 # number of writebacks
|
|
system.iocache.writebacks::total 36190 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
|
|
system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::realview.ide 19255376 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 19255376 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2927396660 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::total 2927396660 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::realview.ide 19255376 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 19255376 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::realview.ide 19255376 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 19255376 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79240.230453 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 79240.230453 # average ReadReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80813.732884 # average WriteLineReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80813.732884 # average WriteLineReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::realview.ide 79240.230453 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 79240.230453 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::realview.ide 79240.230453 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 79240.230453 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.tags.replacements 123618 # number of replacements
|
|
system.l2c.tags.tagsinuse 63093.840837 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 421259 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 187589 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 2.245649 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 13244.114990 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.878668 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.996497 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 7731.277102 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 2849.874177 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 36272.088123 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.954483 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 1120.568935 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 367.321258 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1502.766604 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.202089 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000059 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.117970 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.043486 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.553468 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.017099 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.005605 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.022930 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.962736 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1022 32107 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_blocks::1024 31859 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1022::2 131 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1022::3 4716 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1022::4 27259 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::3 2381 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::4 29068 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1022 0.489914 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.486130 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 5836461 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 5836461 # Number of data accesses
|
|
system.l2c.WritebackDirty_hits::writebacks 257531 # number of WritebackDirty hits
|
|
system.l2c.WritebackDirty_hits::total 257531 # number of WritebackDirty hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 32441 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 1723 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 34164 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu0.data 2115 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu1.data 899 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 3014 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 4177 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 1342 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 5519 # number of ReadExReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 81 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 92 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.inst 28642 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.data 47295 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47544 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 15 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 18 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.inst 6315 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.data 4707 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3005 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::total 137714 # number of ReadSharedReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 81 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 92 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 28642 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 51472 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.l2cache.prefetcher 47544 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 15 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 18 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 6315 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 6049 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.l2cache.prefetcher 3005 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 143233 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 81 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 92 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 28642 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 51472 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.l2cache.prefetcher 47544 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 15 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 18 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 6315 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 6049 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.l2cache.prefetcher 3005 # number of overall hits
|
|
system.l2c.overall_hits::total 143233 # number of overall hits
|
|
system.l2c.UpgradeReq_misses::cpu0.data 9610 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 2300 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 11910 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 655 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu1.data 1322 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 1977 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 11124 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 7851 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 18975 # number of ReadExReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 6 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.inst 17856 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.data 8887 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134682 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.inst 2021 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.data 752 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5338 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::total 169545 # number of ReadSharedReq misses
|
|
system.l2c.demand_misses::cpu0.dtb.walker 6 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.inst 17856 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 20011 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.l2cache.prefetcher 134682 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 2021 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 8603 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.l2cache.prefetcher 5338 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 188520 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.dtb.walker 6 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.inst 17856 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 20011 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.l2cache.prefetcher 134682 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 2021 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 8603 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.l2cache.prefetcher 5338 # number of overall misses
|
|
system.l2c.overall_misses::total 188520 # number of overall misses
|
|
system.l2c.UpgradeReq_miss_latency::cpu0.data 34729000 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 5015500 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 39744500 # number of UpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3979500 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2518000 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::total 6497500 # number of SCUpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 1612676500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 1029832500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 2642509000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 823500 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 272000 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2350559500 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu0.data 1210448500 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 19570272761 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 132500 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu1.inst 268405000 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu1.data 104648000 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 846840628 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::total 24352402389 # number of ReadSharedReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.dtb.walker 823500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.itb.walker 272000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 2350559500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 2823125000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 19570272761 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.dtb.walker 132500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 268405000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 1134480500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 846840628 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 26994911389 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.dtb.walker 823500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.itb.walker 272000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 2350559500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 2823125000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 19570272761 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.dtb.walker 132500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 268405000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 1134480500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 846840628 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 26994911389 # number of overall miss cycles
|
|
system.l2c.WritebackDirty_accesses::writebacks 257531 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2c.WritebackDirty_accesses::total 257531 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 42051 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 4023 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 46074 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 2770 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu1.data 2221 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 4991 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 15301 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 9193 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 24494 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 87 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 94 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.inst 46498 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.data 56182 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 182226 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 16 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 18 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.inst 8336 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.data 5459 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 8343 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::total 307259 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.dtb.walker 87 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.itb.walker 94 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.inst 46498 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 71483 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.l2cache.prefetcher 182226 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.dtb.walker 16 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.itb.walker 18 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 8336 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 14652 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.l2cache.prefetcher 8343 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 331753 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.dtb.walker 87 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.itb.walker 94 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 46498 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 71483 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.l2cache.prefetcher 182226 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.dtb.walker 16 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.itb.walker 18 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 8336 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 14652 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.l2cache.prefetcher 8343 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 331753 # number of overall (read+write) accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.228532 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.571713 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.258497 # miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.236462 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.595227 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::total 0.396113 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.727011 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.854019 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.774680 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.068966 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.021277 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.384017 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.158182 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.739093 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.062500 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.242442 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.137754 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.639818 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::total 0.551798 # miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.068966 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.itb.walker 0.021277 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.384017 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.279941 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.739093 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.062500 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.242442 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.587155 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.639818 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.568254 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.068966 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.itb.walker 0.021277 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.384017 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.279941 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.739093 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.062500 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.242442 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.587155 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.639818 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.568254 # miss rate for overall accesses
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3613.839750 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2180.652174 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 3337.069689 # average UpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6075.572519 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1904.689864 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::total 3286.545271 # average SCUpgradeReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 144972.716649 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131172.143676 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 139262.661397 # average ReadExReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 137250 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 136000 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 131639.756944 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136204.399685 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 145307.262745 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 132500 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 132808.015834 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 139159.574468 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 158643.804421 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::total 143633.857613 # average ReadSharedReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 137250 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 136000 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.inst 131639.756944 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.data 141078.656739 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 145307.262745 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 132500 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 132808.015834 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 131870.335929 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 158643.804421 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 143193.886001 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 137250 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 136000 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.inst 131639.756944 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.data 141078.656739 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 145307.262745 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 132500 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 132808.015834 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 131870.335929 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 158643.804421 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 143193.886001 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.writebacks::writebacks 97095 # number of writebacks
|
|
system.l2c.writebacks::total 97095 # number of writebacks
|
|
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 5 # number of ReadSharedReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::cpu0.data 1 # number of ReadSharedReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 11 # number of ReadSharedReq MSHR hits
|
|
system.l2c.ReadSharedReq_mshr_hits::total 17 # number of ReadSharedReq MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu0.data 1 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu0.data 1 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::total 17 # number of overall MSHR hits
|
|
system.l2c.CleanEvict_mshr_misses::writebacks 2818 # number of CleanEvict MSHR misses
|
|
system.l2c.CleanEvict_mshr_misses::total 2818 # number of CleanEvict MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu0.data 9610 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 2300 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 11910 # number of UpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 655 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1322 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::total 1977 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu0.data 11124 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 7851 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 18975 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 6 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17851 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8886 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 134682 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2010 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 752 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5338 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::total 169528 # number of ReadSharedReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.dtb.walker 6 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.inst 17851 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.data 20010 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134682 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 2010 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 8603 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5338 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 188503 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.dtb.walker 6 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.inst 17851 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.data 20010 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134682 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 2010 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 8603 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5338 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 188503 # number of overall MSHR misses
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31860 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3104 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::total 44163 # number of ReadReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28553 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2430 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::total 30983 # number of WriteReq MSHR uncacheable
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60413 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5534 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::total 75146 # number of overall MSHR uncacheable misses
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 725072500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 172861000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 897933500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 50674000 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 101405500 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::total 152079500 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1501436500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 951322500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 2452759000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 763500 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 252000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2171508000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1121559000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 18223452761 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 122500 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 247283000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 97128000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 793460628 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::total 22655529389 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 763500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 252000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.inst 2171508000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.data 2622995500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 18223452761 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 122500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 247283000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 1048450500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 793460628 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 25108288389 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 763500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 252000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 2171508000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.data 2622995500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 18223452761 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 122500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 247283000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 1048450500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 793460628 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 25108288389 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1023815000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5812758500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 19032500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 349483000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 7205089000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4715021500 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 233050000 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::total 4948071500 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1023815000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10527780000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 19032500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 582533000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 12153160500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.228532 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.571713 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.258497 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.236462 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.595227 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.396113 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.727011 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.854019 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.774680 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.068966 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.021277 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.383909 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.158165 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739093 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.062500 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.241123 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.137754 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.639818 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.551743 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.068966 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.021277 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.383909 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.279927 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739093 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.062500 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.241123 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.587155 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.639818 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.568203 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.068966 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.021277 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.383909 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.279927 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739093 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.062500 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.241123 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.587155 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.639818 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.568203 # mshr miss rate for overall accesses
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75449.791883 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75156.956522 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75393.240974 # average UpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77364.885496 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76706.127080 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76924.380374 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 134972.716649 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121172.143676 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 129262.661397 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 127250 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121646.294325 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126216.407833 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135307.262745 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123026.368159 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129159.574468 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148643.804421 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133638.864312 # average ReadSharedReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 127250 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121646.294325 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131084.232884 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135307.262745 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123026.368159 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121870.335929 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148643.804421 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 133198.349040 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 127250 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121646.294325 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131084.232884 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135307.262745 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123026.368159 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121870.335929 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148643.804421 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 133198.349040 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182446.908349 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 112591.172680 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163147.634898 # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165132.262810 # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 95905.349794 # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159702.788626 # average WriteReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174263.486336 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 105264.365739 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total 161727.310835 # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadReq 44163 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 213934 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 30983 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 30983 # Transaction distribution
|
|
system.membus.trans_dist::WritebackDirty 133285 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 14406 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 73490 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 39839 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 13966 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 39499 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 18896 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 169771 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107934 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14022 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664172 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 786162 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108909 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 108909 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 895071 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162814 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28044 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18307596 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::total 18498522 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 20815642 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 120564 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 581920 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 581920 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 581920 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 88268000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 11611500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer5.occupancy 967762037 # Layer occupancy (ticks)
|
|
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 1134685490 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer3.occupancy 64105002 # Layer occupancy (ticks)
|
|
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
|
|
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
|
|
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
|
|
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
|
|
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
|
|
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
|
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
|
|
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
|
|
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
|
|
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
|
|
system.toL2Bus.snoop_filter.tot_requests 959770 # Total number of requests made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_requests 518663 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_requests 138023 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.snoop_filter.tot_snoops 20272 # Total number of snoops made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_snoops 19432 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_snoops 840 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.trans_dist::ReadReq 44166 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 467162 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 30983 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 30983 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WritebackDirty 390842 # Transaction distribution
|
|
system.toL2Bus.trans_dist::CleanEvict 84262 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 107575 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 42853 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 150428 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 50605 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 50605 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadSharedReq 423011 # Transaction distribution
|
|
system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1226424 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 245800 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 1472224 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34332563 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3643847 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 37976410 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 437847 # Total snoops (count)
|
|
system.toL2Bus.snoop_fanout::samples 895583 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 0.335708 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 0.474219 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 595769 66.52% 66.52% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 298974 33.38% 99.91% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 840 0.09% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 895583 # Request fanout histogram
|
|
system.toL2Bus.reqLayer0.occupancy 863469481 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.snoopLayer0.occupancy 342622 # Layer occupancy (ticks)
|
|
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 647119226 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 200312901 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|