gem5/src
Gabe Black bacbb8ecbc cpu: Only check for PC events on instruction boundaries.
Only the instruction address is actually checked, so there's no need to check
repeatedly while we're working through the microops of a macroop and that's
not changing.
2014-12-05 01:47:35 -08:00
..
arch misc: Make the GDB register cache accessible in various sized chunks. 2014-12-05 01:44:24 -08:00
base misc: Make the GDB register cache accessible in various sized chunks. 2014-12-05 01:44:24 -08:00
cpu cpu: Only check for PC events on instruction boundaries. 2014-12-05 01:47:35 -08:00
dev ide: Accept the IDLE (0xe3) ATA command. 2014-12-03 03:07:35 -08:00
doc cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
doxygen MEM: Put memory system document into doxygen 2012-09-25 11:49:41 -05:00
kern misc: Move AddrRangeList from port.hh to addr_range.hh 2014-10-16 05:49:59 -04:00
mem mem: Support WriteInvalidate (again) 2014-12-02 06:08:19 -05:00
proto mem: change the namespace Message to ProtoMessage 2014-09-01 16:55:46 -05:00
python scons: Ensure dictionary iteration is sorted by key 2014-12-02 06:08:22 -05:00
sim misc: Another round of static analysis fixups 2014-11-24 09:03:38 -05:00
unittest unittest: Fix build errors 2014-01-30 12:21:58 -06:00
Doxyfile Doxygen: Update the version of the Doxyfile 2012-10-11 06:38:42 -04:00
SConscript scons: Ensure dictionary iteration is sorted by key 2014-12-02 06:08:22 -05:00