misc: Make the GDB register cache accessible in various sized chunks.
Not all ISAs have 64 bit sized registers, so it's not always very convenient to access the GDB register cache in 64 bit sized chunks. This change makes it accessible in 8, 16, 32, or 64 bit chunks. The MIPS and ARM implementations were working around that limitation by bundling and unbundling 32 bit values into 64 bit values. That code has been removed.
This commit is contained in:
Gabe Black
parent
7540656fc5
commit
fe48c0a32b
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@ -1,4 +1,5 @@
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/*
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* Copyright 2014 Google, Inc.
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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@ -145,7 +146,7 @@ using namespace std;
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using namespace AlphaISA;
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RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc)
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: BaseRemoteGDB(_system, tc, KGDB_NUMREGS)
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: BaseRemoteGDB(_system, tc, KGDB_NUMREGS * sizeof(uint64_t))
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{
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memset(gdbregs.regs, 0, gdbregs.bytes());
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}
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@ -211,23 +212,20 @@ RemoteGDB::getregs()
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{
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memset(gdbregs.regs, 0, gdbregs.bytes());
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gdbregs.regs[KGDB_REG_PC] = context->pcState().pc();
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gdbregs.regs64[KGDB_REG_PC] = context->pcState().pc();
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// @todo: Currently this is very Alpha specific.
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if (PcPAL(gdbregs.regs[KGDB_REG_PC])) {
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for (int i = 0; i < NumIntArchRegs; ++i) {
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gdbregs.regs[i] = context->readIntReg(reg_redir[i]);
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}
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if (PcPAL(gdbregs.regs64[KGDB_REG_PC])) {
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for (int i = 0; i < NumIntArchRegs; ++i)
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gdbregs.regs64[i] = context->readIntReg(reg_redir[i]);
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} else {
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for (int i = 0; i < NumIntArchRegs; ++i) {
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gdbregs.regs[i] = context->readIntReg(i);
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}
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for (int i = 0; i < NumIntArchRegs; ++i)
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gdbregs.regs64[i] = context->readIntReg(i);
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}
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#ifdef KGDB_FP_REGS
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for (int i = 0; i < NumFloatArchRegs; ++i) {
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gdbregs.regs[i + KGDB_REG_F0] = context->readFloatRegBits(i);
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}
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for (int i = 0; i < NumFloatArchRegs; ++i)
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gdbregs.regs64[i + KGDB_REG_F0] = context->readFloatRegBits(i);
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#endif
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}
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@ -239,22 +237,22 @@ void
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RemoteGDB::setregs()
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{
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// @todo: Currently this is very Alpha specific.
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if (PcPAL(gdbregs.regs[KGDB_REG_PC])) {
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if (PcPAL(gdbregs.regs64[KGDB_REG_PC])) {
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for (int i = 0; i < NumIntArchRegs; ++i) {
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context->setIntReg(reg_redir[i], gdbregs.regs[i]);
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context->setIntReg(reg_redir[i], gdbregs.regs64[i]);
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}
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} else {
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for (int i = 0; i < NumIntArchRegs; ++i) {
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context->setIntReg(i, gdbregs.regs[i]);
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context->setIntReg(i, gdbregs.regs64[i]);
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}
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}
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#ifdef KGDB_FP_REGS
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for (int i = 0; i < NumFloatArchRegs; ++i) {
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context->setFloatRegBits(i, gdbregs.regs[i + KGDB_REG_F0]);
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context->setFloatRegBits(i, gdbregs.regs64[i + KGDB_REG_F0]);
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}
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#endif
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context->pcState(gdbregs.regs[KGDB_REG_PC]);
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context->pcState(gdbregs.regs64[KGDB_REG_PC]);
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}
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void
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@ -1,4 +1,5 @@
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/*
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* Copyright 2014 Google Inc.
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* Copyright (c) 2010, 2013 ARM Limited
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* All rights reserved
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*
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@ -160,7 +161,8 @@ using namespace std;
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using namespace ArmISA;
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RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc)
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: BaseRemoteGDB(_system, tc, MAX_NUMREGS), notTakenBkpt(0), takenBkpt(0)
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: BaseRemoteGDB(_system, tc, GDB_REG_BYTES),
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notTakenBkpt(0), takenBkpt(0)
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{
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}
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@ -207,62 +209,50 @@ RemoteGDB::getregs()
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if (inAArch64(context)) { // AArch64
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// x0-x31
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for (int i = 0; i < 32; ++i) {
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gdbregs.regs[REG_X0 + i] = context->readIntReg(INTREG_X0 + i);
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}
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for (int i = 0; i < 32; ++i)
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gdbregs.regs64[GDB64_X0 + i] = context->readIntReg(INTREG_X0 + i);
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// pc
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gdbregs.regs[REG_PC_64] = context->pcState().pc();
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gdbregs.regs64[GDB64_PC] = context->pcState().pc();
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// cpsr
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gdbregs.regs[REG_CPSR_64] = context->readMiscRegNoEffect(MISCREG_CPSR);
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gdbregs.regs64[GDB64_CPSR] =
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context->readMiscRegNoEffect(MISCREG_CPSR);
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// v0-v31
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for (int i = 0; i < 32; ++i) {
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gdbregs.regs[REG_V0 + 2 * i] = static_cast<uint64_t>(
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context->readFloatRegBits(i * 4 + 3)) << 32 |
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context->readFloatRegBits(i * 4 + 2);
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gdbregs.regs[REG_V0 + 2 * i + 1] = static_cast<uint64_t>(
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context->readFloatRegBits(i * 4 + 1)) << 32 |
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context->readFloatRegBits(i * 4 + 0);
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for (int i = 0; i < 128; i += 4) {
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int gdboff = GDB64_V0_32 + i;
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gdbregs.regs32[gdboff + 0] = context->readFloatRegBits(i + 2);
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gdbregs.regs32[gdboff + 1] = context->readFloatRegBits(i + 3);
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gdbregs.regs32[gdboff + 2] = context->readFloatRegBits(i + 0);
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gdbregs.regs32[gdboff + 3] = context->readFloatRegBits(i + 1);
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}
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} else { // AArch32
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// R0-R15 supervisor mode
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// arm registers are 32 bits wide, gdb registers are 64 bits wide two
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// arm registers are packed into one gdb register (little endian)
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gdbregs.regs[REG_R0 + 0] = context->readIntReg(INTREG_R1) << 32 |
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context->readIntReg(INTREG_R0);
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gdbregs.regs[REG_R0 + 1] = context->readIntReg(INTREG_R3) << 32 |
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context->readIntReg(INTREG_R2);
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gdbregs.regs[REG_R0 + 2] = context->readIntReg(INTREG_R5) << 32 |
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context->readIntReg(INTREG_R4);
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gdbregs.regs[REG_R0 + 3] = context->readIntReg(INTREG_R7) << 32 |
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context->readIntReg(INTREG_R6);
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gdbregs.regs[REG_R0 + 4] = context->readIntReg(INTREG_R9) << 32 |
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context->readIntReg(INTREG_R8);
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gdbregs.regs[REG_R0 + 5] = context->readIntReg(INTREG_R11) << 32|
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context->readIntReg(INTREG_R10);
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gdbregs.regs[REG_R0 + 6] = context->readIntReg(INTREG_SP) << 32 |
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context->readIntReg(INTREG_R12);
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gdbregs.regs[REG_R0 + 7] = context->pcState().pc() << 32 |
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context->readIntReg(INTREG_LR);
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gdbregs.regs32[GDB32_R0 + 0] = context->readIntReg(INTREG_R0);
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gdbregs.regs32[GDB32_R0 + 1] = context->readIntReg(INTREG_R1);
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gdbregs.regs32[GDB32_R0 + 2] = context->readIntReg(INTREG_R2);
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gdbregs.regs32[GDB32_R0 + 3] = context->readIntReg(INTREG_R3);
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gdbregs.regs32[GDB32_R0 + 4] = context->readIntReg(INTREG_R4);
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gdbregs.regs32[GDB32_R0 + 5] = context->readIntReg(INTREG_R5);
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gdbregs.regs32[GDB32_R0 + 6] = context->readIntReg(INTREG_R6);
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gdbregs.regs32[GDB32_R0 + 7] = context->readIntReg(INTREG_R7);
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gdbregs.regs32[GDB32_R0 + 8] = context->readIntReg(INTREG_R8);
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gdbregs.regs32[GDB32_R0 + 9] = context->readIntReg(INTREG_R9);
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gdbregs.regs32[GDB32_R0 + 10] = context->readIntReg(INTREG_R10);
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gdbregs.regs32[GDB32_R0 + 11] = context->readIntReg(INTREG_R11);
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gdbregs.regs32[GDB32_R0 + 12] = context->readIntReg(INTREG_R12);
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gdbregs.regs32[GDB32_R0 + 13] = context->readIntReg(INTREG_SP);
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gdbregs.regs32[GDB32_R0 + 14] = context->readIntReg(INTREG_LR);
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gdbregs.regs32[GDB32_R0 + 15] = context->pcState().pc();
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// CPSR
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gdbregs.regs[REG_CPSR] = context->readMiscRegNoEffect(MISCREG_CPSR);
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gdbregs.regs32[GDB32_CPSR] = context->readMiscRegNoEffect(MISCREG_CPSR);
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// vfpv3/neon floating point registers (32 double or 64 float)
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gdbregs.regs[REG_F0] =
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static_cast<uint64_t>(context->readFloatRegBits(0)) << 32 |
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gdbregs.regs[REG_CPSR];
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for (int i = 1; i < (NumFloatV7ArchRegs>>1); ++i) {
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gdbregs.regs[i + REG_F0] =
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static_cast<uint64_t>(context->readFloatRegBits(2*i)) << 32 |
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context->readFloatRegBits(2*i-1);
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}
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for (int i = 0; i < NumFloatV7ArchRegs; ++i)
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gdbregs.regs32[GDB32_F0 + i] = context->readFloatRegBits(i);
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// FPSCR
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gdbregs.regs[REG_FPSCR] = static_cast<uint64_t>(
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context->readMiscRegNoEffect(MISCREG_FPSCR)) << 32 |
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context->readFloatRegBits(NumFloatV7ArchRegs - 1);
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gdbregs.regs32[GDB32_FPSCR] =
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context->readMiscRegNoEffect(MISCREG_FPSCR);
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}
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}
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@ -277,63 +267,50 @@ RemoteGDB::setregs()
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DPRINTF(GDBAcc, "setregs in remotegdb \n");
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if (inAArch64(context)) { // AArch64
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// x0-x31
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for (int i = 0; i < 32; ++i) {
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context->setIntReg(INTREG_X0 + i, gdbregs.regs[REG_X0 + i]);
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}
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for (int i = 0; i < 32; ++i)
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context->setIntReg(INTREG_X0 + i, gdbregs.regs64[GDB64_X0 + i]);
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// pc
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context->pcState(gdbregs.regs[REG_PC_64]);
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context->pcState(gdbregs.regs64[GDB64_PC]);
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// cpsr
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context->setMiscRegNoEffect(MISCREG_CPSR, gdbregs.regs[REG_CPSR_64]);
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context->setMiscRegNoEffect(MISCREG_CPSR, gdbregs.regs64[GDB64_CPSR]);
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// v0-v31
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for (int i = 0; i < 32; ++i) {
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context->setFloatRegBits(i * 4 + 3,
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gdbregs.regs[REG_V0 + 2 * i] >> 32);
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context->setFloatRegBits(i * 4 + 2,
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gdbregs.regs[REG_V0 + 2 * i]);
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context->setFloatRegBits(i * 4 + 1,
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gdbregs.regs[REG_V0 + 2 * i + 1] >> 32);
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context->setFloatRegBits(i * 4 + 0,
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gdbregs.regs[REG_V0 + 2 * i + 1]);
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for (int i = 0; i < 128; i += 4) {
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int gdboff = GDB64_V0_32 + i;
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context->setFloatRegBits(i + 2, gdbregs.regs32[gdboff + 0]);
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context->setFloatRegBits(i + 3, gdbregs.regs32[gdboff + 1]);
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context->setFloatRegBits(i + 0, gdbregs.regs32[gdboff + 2]);
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context->setFloatRegBits(i + 1, gdbregs.regs32[gdboff + 3]);
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}
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} else { // AArch32
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// R0-R15 supervisor mode
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// arm registers are 32 bits wide, gdb registers are 64 bits wide
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// two arm registers are packed into one gdb register (little endian)
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context->setIntReg(INTREG_R0 , bits(gdbregs.regs[REG_R0 + 0], 31, 0));
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context->setIntReg(INTREG_R1 , bits(gdbregs.regs[REG_R0 + 0], 63, 32));
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context->setIntReg(INTREG_R2 , bits(gdbregs.regs[REG_R0 + 1], 31, 0));
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context->setIntReg(INTREG_R3 , bits(gdbregs.regs[REG_R0 + 1], 63, 32));
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context->setIntReg(INTREG_R4 , bits(gdbregs.regs[REG_R0 + 2], 31, 0));
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context->setIntReg(INTREG_R5 , bits(gdbregs.regs[REG_R0 + 2], 63, 32));
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context->setIntReg(INTREG_R6 , bits(gdbregs.regs[REG_R0 + 3], 31, 0));
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context->setIntReg(INTREG_R7 , bits(gdbregs.regs[REG_R0 + 3], 63, 32));
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context->setIntReg(INTREG_R8 , bits(gdbregs.regs[REG_R0 + 4], 31, 0));
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context->setIntReg(INTREG_R9 , bits(gdbregs.regs[REG_R0 + 4], 63, 32));
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context->setIntReg(INTREG_R10, bits(gdbregs.regs[REG_R0 + 5], 31, 0));
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context->setIntReg(INTREG_R11, bits(gdbregs.regs[REG_R0 + 5], 63, 32));
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context->setIntReg(INTREG_R12, bits(gdbregs.regs[REG_R0 + 6], 31, 0));
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context->setIntReg(INTREG_SP , bits(gdbregs.regs[REG_R0 + 6], 63, 32));
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context->setIntReg(INTREG_LR , bits(gdbregs.regs[REG_R0 + 7], 31, 0));
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context->pcState(bits(gdbregs.regs[REG_R0 + 7], 63, 32));
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context->setIntReg(INTREG_R0, gdbregs.regs32[GDB32_R0 + 0]);
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context->setIntReg(INTREG_R1, gdbregs.regs32[GDB32_R0 + 1]);
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context->setIntReg(INTREG_R2, gdbregs.regs32[GDB32_R0 + 2]);
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context->setIntReg(INTREG_R3, gdbregs.regs32[GDB32_R0 + 3]);
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context->setIntReg(INTREG_R4, gdbregs.regs32[GDB32_R0 + 4]);
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context->setIntReg(INTREG_R5, gdbregs.regs32[GDB32_R0 + 5]);
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context->setIntReg(INTREG_R6, gdbregs.regs32[GDB32_R0 + 6]);
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context->setIntReg(INTREG_R7, gdbregs.regs32[GDB32_R0 + 7]);
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context->setIntReg(INTREG_R8, gdbregs.regs32[GDB32_R0 + 8]);
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context->setIntReg(INTREG_R9, gdbregs.regs32[GDB32_R0 + 9]);
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context->setIntReg(INTREG_R10, gdbregs.regs32[GDB32_R0 + 10]);
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context->setIntReg(INTREG_R11, gdbregs.regs32[GDB32_R0 + 11]);
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context->setIntReg(INTREG_R12, gdbregs.regs32[GDB32_R0 + 12]);
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context->setIntReg(INTREG_SP, gdbregs.regs32[GDB32_R0 + 13]);
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context->setIntReg(INTREG_LR, gdbregs.regs32[GDB32_R0 + 14]);
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context->pcState(gdbregs.regs32[GDB32_R0 + 7]);
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//CPSR
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context->setMiscRegNoEffect(MISCREG_CPSR, gdbregs.regs[REG_CPSR]);
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context->setMiscRegNoEffect(MISCREG_CPSR, gdbregs.regs32[GDB32_CPSR]);
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//vfpv3/neon floating point registers (32 double or 64 float)
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context->setFloatRegBits(0, gdbregs.regs[REG_F0]>>32);
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for (int i = 1; i < NumFloatV7ArchRegs; ++i) {
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if (i%2) {
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int j = (i+1)/2;
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context->setFloatRegBits(i, bits(gdbregs.regs[j + REG_F0], 31, 0));
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} else {
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int j = i/2;
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context->setFloatRegBits(i, gdbregs.regs[j + REG_F0]>>32);
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}
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}
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for (int i = 0; i < NumFloatV7ArchRegs; ++i)
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context->setFloatRegBits(i, gdbregs.regs32[GDB32_F0 + i]);
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//FPSCR
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context->setMiscReg(MISCREG_FPSCR, gdbregs.regs[REG_FPSCR]>>32);
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context->setMiscReg(MISCREG_FPSCR, gdbregs.regs32[GDB32_FPSCR]);
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}
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}
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@ -1,4 +1,5 @@
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/*
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* Copyright 2014 Google, Inc.
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* Copyright (c) 2013 ARM Limited
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* All rights reserved
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*
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@ -45,6 +46,8 @@
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#ifndef __ARCH_ARM_REMOTE_GDB_HH__
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#define __ARCH_ARM_REMOTE_GDB_HH__
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#include <algorithm>
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#include "base/remote_gdb.hh"
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class System;
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@ -54,21 +57,26 @@ namespace ArmISA
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{
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// AArch32 registers with vfpv3/neon
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const int NUMREGS = 41; /* r0-r15, cpsr, d0-d31, fpscr */
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const int REG_R0 = 0;
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const int REG_F0 = 8;
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const int REG_CPSR = 8; /* bit 512 to bit 543 */
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const int REG_FPSCR = 40; /* bit 2592 to bit 2623 */
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enum {
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GDB32_R0 = 0,
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GDB32_CPSR = 16,
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GDB32_F0 = 17,
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GDB32_FPSCR = 81,
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GDB32_NUMREGS = 82
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};
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// AArch64 registers
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const int NUMREGS_64 = 98; // x0-x31, pc, cpsr (64-bit GPRs)
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// v0-v31 (128-bit FPRs)
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const int REG_X0 = 0;
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const int REG_PC_64 = 32;
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const int REG_CPSR_64 = 33;
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const int REG_V0 = 34;
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enum {
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GDB64_X0 = 0,
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GDB64_PC = 32,
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GDB64_CPSR = 33,
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GDB64_V0 = 34,
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GDB64_V0_32 = 2 * GDB64_V0,
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GDB64_NUMREGS = 98
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};
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const int MAX_NUMREGS = NUMREGS_64;
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const int GDB_REG_BYTES = std::max(GDB64_NUMREGS * sizeof(uint64_t),
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GDB32_NUMREGS * sizeof(uint32_t));
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class RemoteGDB : public BaseRemoteGDB
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{
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@ -1,4 +1,5 @@
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/*
|
||||
* Copyright 2014 Google, Inc.
|
||||
* Copyright (c) 2010 ARM Limited
|
||||
* All rights reserved
|
||||
*
|
||||
|
|
@ -148,7 +149,7 @@ using namespace std;
|
|||
using namespace MipsISA;
|
||||
|
||||
RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc)
|
||||
: BaseRemoteGDB(_system, tc, GdbNumRegs)
|
||||
: BaseRemoteGDB(_system, tc, GdbNumRegs * sizeof(uint32_t))
|
||||
{
|
||||
}
|
||||
|
||||
|
|
@ -181,31 +182,26 @@ RemoteGDB::getregs()
|
|||
// two MIPS registers are packed into one gdb register (little endian)
|
||||
|
||||
// INTREG: R0~R31
|
||||
for (int i = 0; i < GdbIntArchRegs; i++) {
|
||||
gdbregs.regs[i] = pack(
|
||||
context->readIntReg(i * 2),
|
||||
context->readIntReg(i * 2 + 1));
|
||||
}
|
||||
for (int i = 0; i < GdbIntArchRegs; i++)
|
||||
gdbregs.regs32[i] = context->readIntReg(i);
|
||||
// SR, LO, HI, BADVADDR, CAUSE, PC
|
||||
gdbregs.regs[GdbIntArchRegs + 0] = pack(
|
||||
context->readMiscRegNoEffect(MISCREG_STATUS),
|
||||
context->readIntReg(INTREG_LO));
|
||||
gdbregs.regs[GdbIntArchRegs + 1] = pack(
|
||||
context->readIntReg(INTREG_HI),
|
||||
context->readMiscRegNoEffect(MISCREG_BADVADDR));
|
||||
gdbregs.regs[GdbIntArchRegs + 2] = pack(
|
||||
context->readMiscRegNoEffect(MISCREG_CAUSE),
|
||||
context->pcState().pc());
|
||||
gdbregs.regs32[GdbIntArchRegs + 0] =
|
||||
context->readMiscRegNoEffect(MISCREG_STATUS);
|
||||
gdbregs.regs32[GdbIntArchRegs + 1] = context->readIntReg(INTREG_LO);
|
||||
gdbregs.regs32[GdbIntArchRegs + 2] = context->readIntReg(INTREG_HI);
|
||||
gdbregs.regs32[GdbIntArchRegs + 3] =
|
||||
context->readMiscRegNoEffect(MISCREG_BADVADDR);
|
||||
gdbregs.regs32[GdbIntArchRegs + 4] =
|
||||
context->readMiscRegNoEffect(MISCREG_CAUSE);
|
||||
gdbregs.regs32[GdbIntArchRegs + 5] = context->pcState().pc();
|
||||
// FLOATREG: F0~F31
|
||||
for (int i = 0; i < GdbFloatArchRegs; i++) {
|
||||
gdbregs.regs[GdbIntRegs + i] = pack(
|
||||
context->readFloatRegBits(i * 2),
|
||||
context->readFloatRegBits(i * 2 + 1));
|
||||
}
|
||||
for (int i = 0; i < GdbFloatArchRegs; i++)
|
||||
gdbregs.regs32[GdbIntRegs + i] = context->readFloatRegBits(i);
|
||||
// FCR, FIR
|
||||
gdbregs.regs[GdbIntRegs + GdbFloatArchRegs + 0] = pack(
|
||||
context->readFloatRegBits(FLOATREG_FCCR),
|
||||
context->readFloatRegBits(FLOATREG_FIR));
|
||||
gdbregs.regs32[GdbIntRegs + GdbFloatArchRegs + 0] =
|
||||
context->readFloatRegBits(FLOATREG_FCCR);
|
||||
gdbregs.regs32[GdbIntRegs + GdbFloatArchRegs + 1] =
|
||||
context->readFloatRegBits(FLOATREG_FIR);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -217,41 +213,27 @@ RemoteGDB::setregs()
|
|||
{
|
||||
DPRINTF(GDBAcc, "setregs in remotegdb \n");
|
||||
|
||||
// MIPS registers are 32 bits wide, gdb registers are 64 bits wide
|
||||
// two MIPS registers are packed into one gdb register (little endian)
|
||||
|
||||
// INTREG: R0~R31
|
||||
for (int i = 0; i < GdbIntArchRegs; i++) {
|
||||
if (i) context->setIntReg(i * 2,
|
||||
unpackLo(gdbregs.regs[i]));
|
||||
context->setIntReg(i * 2 + 1,
|
||||
unpackHi(gdbregs.regs[i]));
|
||||
}
|
||||
for (int i = 1; i < GdbIntArchRegs; i++)
|
||||
context->setIntReg(i, gdbregs.regs32[i]);
|
||||
// SR, LO, HI, BADVADDR, CAUSE, PC
|
||||
context->setMiscRegNoEffect(MISCREG_STATUS,
|
||||
unpackLo(gdbregs.regs[GdbIntArchRegs + 0]));
|
||||
context->setIntReg(INTREG_LO,
|
||||
unpackHi(gdbregs.regs[GdbIntArchRegs + 0]));
|
||||
context->setIntReg(INTREG_HI,
|
||||
unpackLo(gdbregs.regs[GdbIntArchRegs + 1]));
|
||||
gdbregs.regs32[GdbIntArchRegs + 0]);
|
||||
context->setIntReg(INTREG_LO, gdbregs.regs32[GdbIntArchRegs + 1]);
|
||||
context->setIntReg(INTREG_HI, gdbregs.regs32[GdbIntArchRegs + 2]);
|
||||
context->setMiscRegNoEffect(MISCREG_BADVADDR,
|
||||
unpackHi(gdbregs.regs[GdbIntArchRegs + 1]));
|
||||
gdbregs.regs32[GdbIntArchRegs + 3]);
|
||||
context->setMiscRegNoEffect(MISCREG_CAUSE,
|
||||
unpackLo(gdbregs.regs[GdbIntArchRegs + 2]));
|
||||
context->pcState(
|
||||
unpackHi(gdbregs.regs[GdbIntArchRegs + 2]));
|
||||
gdbregs.regs32[GdbIntArchRegs + 4]);
|
||||
context->pcState(gdbregs.regs32[GdbIntArchRegs + 5]);
|
||||
// FLOATREG: F0~F31
|
||||
for (int i = 0; i < GdbFloatArchRegs; i++) {
|
||||
context->setFloatRegBits(i * 2,
|
||||
unpackLo(gdbregs.regs[GdbIntRegs + i]));
|
||||
context->setFloatRegBits(i * 2 + 1,
|
||||
unpackHi(gdbregs.regs[GdbIntRegs + i]));
|
||||
}
|
||||
for (int i = 0; i < GdbFloatArchRegs; i++)
|
||||
context->setFloatRegBits(i, gdbregs.regs32[GdbIntRegs + i]);
|
||||
// FCR, FIR
|
||||
context->setFloatRegBits(FLOATREG_FCCR,
|
||||
unpackLo(gdbregs.regs[GdbIntRegs + GdbFloatArchRegs + 0]));
|
||||
gdbregs.regs32[GdbIntRegs + GdbFloatArchRegs + 0]);
|
||||
context->setFloatRegBits(FLOATREG_FIR,
|
||||
unpackHi(gdbregs.regs[GdbIntRegs + GdbFloatArchRegs + 0]));
|
||||
gdbregs.regs32[GdbIntRegs + GdbFloatArchRegs + 1]);
|
||||
}
|
||||
|
||||
void
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
/*
|
||||
* Copyright 2014 Google, Inc.
|
||||
* Copyright (c) 2007 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
|
|
@ -42,11 +43,10 @@ namespace MipsISA
|
|||
{
|
||||
|
||||
// The number of special regs depends on gdb.
|
||||
// Two 32-bit regs are packed into one 64-bit reg.
|
||||
const int GdbIntArchRegs = NumIntArchRegs / 2;
|
||||
const int GdbIntSpecialRegs = 6 / 2;
|
||||
const int GdbFloatArchRegs = NumFloatArchRegs / 2;
|
||||
const int GdbFloatSpecialRegs = 2 / 2;
|
||||
const int GdbIntArchRegs = NumIntArchRegs;
|
||||
const int GdbIntSpecialRegs = 6;
|
||||
const int GdbFloatArchRegs = NumFloatArchRegs;
|
||||
const int GdbFloatSpecialRegs = 2;
|
||||
|
||||
const int GdbIntRegs = GdbIntArchRegs + GdbIntSpecialRegs;
|
||||
const int GdbFloatRegs = GdbFloatArchRegs + GdbFloatSpecialRegs;
|
||||
|
|
@ -69,23 +69,6 @@ namespace MipsISA
|
|||
|
||||
void clearSingleStep();
|
||||
void setSingleStep();
|
||||
|
||||
private:
|
||||
uint64_t
|
||||
pack(uint32_t lo, uint32_t hi)
|
||||
{
|
||||
return static_cast<uint64_t>(hi) << 32 | lo;
|
||||
}
|
||||
uint32_t
|
||||
unpackLo(uint64_t val)
|
||||
{
|
||||
return bits(val, 31, 0);
|
||||
}
|
||||
uint32_t
|
||||
unpackHi(uint64_t val)
|
||||
{
|
||||
return bits(val, 63, 32);
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
/*
|
||||
* Copyright 2014 Google, Inc.
|
||||
* Copyright (c) 2002-2005 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
|
|
@ -143,7 +144,7 @@ using namespace std;
|
|||
using namespace SparcISA;
|
||||
|
||||
RemoteGDB::RemoteGDB(System *_system, ThreadContext *c)
|
||||
: BaseRemoteGDB(_system, c, NumGDBRegs), nextBkpt(0)
|
||||
: BaseRemoteGDB(_system, c, NumGDBRegs * sizeof(uint64_t)), nextBkpt(0)
|
||||
{}
|
||||
|
||||
///////////////////////////////////////////////////////////
|
||||
|
|
@ -185,34 +186,35 @@ RemoteGDB::getregs()
|
|||
PSTATE pstate = context->readMiscReg(MISCREG_PSTATE);
|
||||
|
||||
if (pstate.am) {
|
||||
uint32_t *regs;
|
||||
regs = (uint32_t*)gdbregs.regs;
|
||||
regs[Reg32Pc] = htobe((uint32_t)pc.pc());
|
||||
regs[Reg32Npc] = htobe((uint32_t)pc.npc());
|
||||
gdbregs.regs32[Reg32Pc] = htobe((uint32_t)pc.pc());
|
||||
gdbregs.regs32[Reg32Npc] = htobe((uint32_t)pc.npc());
|
||||
for (int x = RegG0; x <= RegI0 + 7; x++)
|
||||
regs[x] = htobe((uint32_t)context->readIntReg(x - RegG0));
|
||||
gdbregs.regs32[x] = htobe((uint32_t)context->readIntReg(x - RegG0));
|
||||
|
||||
regs[Reg32Y] = htobe((uint32_t)context->readIntReg(NumIntArchRegs + 1));
|
||||
regs[Reg32Psr] = htobe((uint32_t)pstate);
|
||||
regs[Reg32Fsr] = htobe((uint32_t)context->readMiscReg(MISCREG_FSR));
|
||||
regs[Reg32Csr] = htobe((uint32_t)context->readIntReg(NumIntArchRegs + 2));
|
||||
gdbregs.regs32[Reg32Y] =
|
||||
htobe((uint32_t)context->readIntReg(NumIntArchRegs + 1));
|
||||
gdbregs.regs32[Reg32Psr] = htobe((uint32_t)pstate);
|
||||
gdbregs.regs32[Reg32Fsr] =
|
||||
htobe((uint32_t)context->readMiscReg(MISCREG_FSR));
|
||||
gdbregs.regs32[Reg32Csr] =
|
||||
htobe((uint32_t)context->readIntReg(NumIntArchRegs + 2));
|
||||
} else {
|
||||
gdbregs.regs[RegPc] = htobe(pc.pc());
|
||||
gdbregs.regs[RegNpc] = htobe(pc.npc());
|
||||
gdbregs.regs64[RegPc] = htobe(pc.pc());
|
||||
gdbregs.regs64[RegNpc] = htobe(pc.npc());
|
||||
for (int x = RegG0; x <= RegI0 + 7; x++)
|
||||
gdbregs.regs[x] = htobe(context->readIntReg(x - RegG0));
|
||||
gdbregs.regs64[x] = htobe(context->readIntReg(x - RegG0));
|
||||
|
||||
gdbregs.regs[RegFsr] = htobe(context->readMiscReg(MISCREG_FSR));
|
||||
gdbregs.regs[RegFprs] = htobe(context->readMiscReg(MISCREG_FPRS));
|
||||
gdbregs.regs[RegY] = htobe(context->readIntReg(NumIntArchRegs + 1));
|
||||
gdbregs.regs[RegState] = htobe(
|
||||
gdbregs.regs64[RegFsr] = htobe(context->readMiscReg(MISCREG_FSR));
|
||||
gdbregs.regs64[RegFprs] = htobe(context->readMiscReg(MISCREG_FPRS));
|
||||
gdbregs.regs64[RegY] = htobe(context->readIntReg(NumIntArchRegs + 1));
|
||||
gdbregs.regs64[RegState] = htobe(
|
||||
context->readMiscReg(MISCREG_CWP) |
|
||||
pstate << 8 |
|
||||
context->readMiscReg(MISCREG_ASI) << 24 |
|
||||
context->readIntReg(NumIntArchRegs + 2) << 32);
|
||||
}
|
||||
|
||||
DPRINTF(GDBRead, "PC=%#x\n", gdbregs.regs[RegPc]);
|
||||
DPRINTF(GDBRead, "PC=%#x\n", gdbregs.regs64[RegPc]);
|
||||
|
||||
// Floating point registers are left at 0 in netbsd
|
||||
// All registers other than the pc, npc and int regs
|
||||
|
|
@ -229,14 +231,14 @@ void
|
|||
RemoteGDB::setregs()
|
||||
{
|
||||
PCState pc;
|
||||
pc.pc(gdbregs.regs[RegPc]);
|
||||
pc.npc(gdbregs.regs[RegNpc]);
|
||||
pc.pc(gdbregs.regs64[RegPc]);
|
||||
pc.npc(gdbregs.regs64[RegNpc]);
|
||||
pc.nnpc(pc.npc() + sizeof(MachInst));
|
||||
pc.upc(0);
|
||||
pc.nupc(1);
|
||||
context->pcState(pc);
|
||||
for (int x = RegG0; x <= RegI0 + 7; x++)
|
||||
context->setIntReg(x - RegG0, gdbregs.regs[x]);
|
||||
context->setIntReg(x - RegG0, gdbregs.regs64[x]);
|
||||
// Only the integer registers, pc and npc are set in netbsd
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
/*
|
||||
* Copyright 2014 Google, Inc.
|
||||
* Copyright (c) 2002-2005 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
|
|
@ -36,6 +37,7 @@
|
|||
#include <map>
|
||||
|
||||
#include "arch/types.hh"
|
||||
#include "base/intmath.hh"
|
||||
#include "base/pollevent.hh"
|
||||
#include "base/socket.hh"
|
||||
#include "cpu/pc_event.hh"
|
||||
|
|
@ -136,16 +138,25 @@ class BaseRemoteGDB
|
|||
class GdbRegCache
|
||||
{
|
||||
public:
|
||||
GdbRegCache(size_t newSize) : regs(new uint64_t[newSize]), size(newSize)
|
||||
GdbRegCache(size_t newSize) :
|
||||
regs64(new uint64_t[divCeil(newSize, sizeof(uint64_t))]),
|
||||
size(newSize)
|
||||
{}
|
||||
~GdbRegCache()
|
||||
{
|
||||
delete [] regs;
|
||||
delete [] regs64;
|
||||
}
|
||||
|
||||
uint64_t * regs;
|
||||
union {
|
||||
uint64_t *regs64;
|
||||
uint32_t *regs32;
|
||||
uint16_t *regs16;
|
||||
uint8_t *regs8;
|
||||
void *regs;
|
||||
};
|
||||
// Size of cache in bytes.
|
||||
size_t size;
|
||||
size_t bytes() { return size * sizeof(uint64_t); }
|
||||
size_t bytes() { return size; }
|
||||
};
|
||||
|
||||
GdbRegCache gdbregs;
|
||||
|
|
|
|||
Loading…
Reference in a new issue