5a15909bac
This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
825 lines
89 KiB
Plaintext
825 lines
89 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000250 # Number of seconds simulated
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sim_ticks 250015500 # Number of ticks simulated
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final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 3032804 # Simulator instruction rate (inst/s)
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host_op_rate 3032728 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 379104441 # Simulator tick rate (ticks/s)
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host_mem_usage 1154504 # Number of bytes of host memory used
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host_seconds 0.66 # Real time elapsed on the host
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sim_insts 2000004 # Number of instructions simulated
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sim_ops 2000004 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 29056 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 25792 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 29056 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.inst 25792 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.data 29056 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu3.inst 25792 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu3.data 29056 # Number of bytes read from this memory
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system.physmem.bytes_read::total 219392 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 25792 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 25792 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu2.inst 25792 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu3.inst 25792 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 103168 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu0.inst 403 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 454 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 403 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 454 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.inst 403 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.data 454 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu3.inst 403 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu3.data 454 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 3428 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu0.inst 103161604 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 116216795 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 103161604 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 116216795 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.inst 103161604 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.data 116216795 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu3.inst 103161604 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu3.data 116216795 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 877513594 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 103161604 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 103161604 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu2.inst 103161604 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu3.inst 103161604 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 412646416 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 103161604 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 116216795 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 103161604 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 116216795 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.inst 103161604 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.data 116216795 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu3.inst 103161604 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu3.data 116216795 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 877513594 # Total bandwidth to/from this memory (bytes/s)
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system.membus.throughput 877513594 # Throughput (bytes/s)
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system.membus.data_through_bus 219392 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.toL2Bus.throughput 977859373 # Throughput (bytes/s)
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system.toL2Bus.data_through_bus 244480 # Total data (bytes)
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system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.cpu0.dtb.fetch_hits 0 # ITB hits
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system.cpu0.dtb.fetch_misses 0 # ITB misses
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system.cpu0.dtb.fetch_acv 0 # ITB acv
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system.cpu0.dtb.fetch_accesses 0 # ITB accesses
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system.cpu0.dtb.read_hits 124435 # DTB read hits
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system.cpu0.dtb.read_misses 8 # DTB read misses
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system.cpu0.dtb.read_acv 0 # DTB read access violations
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system.cpu0.dtb.read_accesses 124443 # DTB read accesses
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system.cpu0.dtb.write_hits 56340 # DTB write hits
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system.cpu0.dtb.write_misses 10 # DTB write misses
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system.cpu0.dtb.write_acv 0 # DTB write access violations
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system.cpu0.dtb.write_accesses 56350 # DTB write accesses
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system.cpu0.dtb.data_hits 180775 # DTB hits
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system.cpu0.dtb.data_misses 18 # DTB misses
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system.cpu0.dtb.data_acv 0 # DTB access violations
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system.cpu0.dtb.data_accesses 180793 # DTB accesses
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system.cpu0.itb.fetch_hits 500019 # ITB hits
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system.cpu0.itb.fetch_misses 13 # ITB misses
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system.cpu0.itb.fetch_acv 0 # ITB acv
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system.cpu0.itb.fetch_accesses 500032 # ITB accesses
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system.cpu0.itb.read_hits 0 # DTB read hits
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system.cpu0.itb.read_misses 0 # DTB read misses
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system.cpu0.itb.read_acv 0 # DTB read access violations
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system.cpu0.itb.read_accesses 0 # DTB read accesses
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system.cpu0.itb.write_hits 0 # DTB write hits
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system.cpu0.itb.write_misses 0 # DTB write misses
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system.cpu0.itb.write_acv 0 # DTB write access violations
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system.cpu0.itb.write_accesses 0 # DTB write accesses
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system.cpu0.itb.data_hits 0 # DTB hits
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system.cpu0.itb.data_misses 0 # DTB misses
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system.cpu0.itb.data_acv 0 # DTB access violations
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system.cpu0.itb.data_accesses 0 # DTB accesses
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system.cpu0.workload.num_syscalls 18 # Number of system calls
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system.cpu0.numCycles 500032 # number of cpu cycles simulated
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu0.committedInsts 500001 # Number of instructions committed
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system.cpu0.committedOps 500001 # Number of ops (including micro ops) committed
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system.cpu0.num_int_alu_accesses 474689 # Number of integer alu accesses
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system.cpu0.num_fp_alu_accesses 32 # Number of float alu accesses
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system.cpu0.num_func_calls 14357 # number of times a function call or return occured
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system.cpu0.num_conditional_control_insts 38180 # number of instructions that are conditional controls
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system.cpu0.num_int_insts 474689 # number of integer instructions
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system.cpu0.num_fp_insts 32 # number of float instructions
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system.cpu0.num_int_register_reads 654286 # number of times the integer registers were read
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system.cpu0.num_int_register_writes 371542 # number of times the integer registers were written
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system.cpu0.num_fp_register_reads 32 # number of times the floating registers were read
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system.cpu0.num_fp_register_writes 16 # number of times the floating registers were written
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system.cpu0.num_mem_refs 180793 # number of memory refs
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system.cpu0.num_load_insts 124443 # Number of load instructions
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system.cpu0.num_store_insts 56350 # Number of store instructions
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system.cpu0.num_idle_cycles 0 # Number of idle cycles
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system.cpu0.num_busy_cycles 500032 # Number of busy cycles
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system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu0.idle_fraction 0 # Percentage of idle cycles
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system.cpu0.icache.tags.replacements 152 # number of replacements
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system.cpu0.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
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system.cpu0.icache.tags.total_refs 499556 # Total number of references to valid blocks.
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system.cpu0.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
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system.cpu0.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks.
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system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu0.icache.tags.occ_blocks::cpu0.inst 218.086151 # Average occupied blocks per requestor
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system.cpu0.icache.tags.occ_percent::cpu0.inst 0.425950 # Average percentage of cache occupancy
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system.cpu0.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy
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system.cpu0.icache.ReadReq_hits::cpu0.inst 499556 # number of ReadReq hits
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system.cpu0.icache.ReadReq_hits::total 499556 # number of ReadReq hits
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system.cpu0.icache.demand_hits::cpu0.inst 499556 # number of demand (read+write) hits
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system.cpu0.icache.demand_hits::total 499556 # number of demand (read+write) hits
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system.cpu0.icache.overall_hits::cpu0.inst 499556 # number of overall hits
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system.cpu0.icache.overall_hits::total 499556 # number of overall hits
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system.cpu0.icache.ReadReq_misses::cpu0.inst 463 # number of ReadReq misses
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system.cpu0.icache.ReadReq_misses::total 463 # number of ReadReq misses
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system.cpu0.icache.demand_misses::cpu0.inst 463 # number of demand (read+write) misses
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system.cpu0.icache.demand_misses::total 463 # number of demand (read+write) misses
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system.cpu0.icache.overall_misses::cpu0.inst 463 # number of overall misses
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system.cpu0.icache.overall_misses::total 463 # number of overall misses
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system.cpu0.icache.ReadReq_accesses::cpu0.inst 500019 # number of ReadReq accesses(hits+misses)
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system.cpu0.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses)
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system.cpu0.icache.demand_accesses::cpu0.inst 500019 # number of demand (read+write) accesses
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system.cpu0.icache.demand_accesses::total 500019 # number of demand (read+write) accesses
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system.cpu0.icache.overall_accesses::cpu0.inst 500019 # number of overall (read+write) accesses
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system.cpu0.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
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system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.000926 # miss rate for ReadReq accesses
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system.cpu0.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
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system.cpu0.icache.demand_miss_rate::cpu0.inst 0.000926 # miss rate for demand accesses
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system.cpu0.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
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system.cpu0.icache.overall_miss_rate::cpu0.inst 0.000926 # miss rate for overall accesses
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system.cpu0.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
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system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu0.icache.fast_writes 0 # number of fast writes performed
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system.cpu0.icache.cache_copies 0 # number of cache copies performed
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system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.dcache.tags.replacements 61 # number of replacements
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system.cpu0.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use
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system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
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system.cpu0.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
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system.cpu0.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks.
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system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu0.dcache.tags.occ_blocks::cpu0.data 276.872320 # Average occupied blocks per requestor
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system.cpu0.dcache.tags.occ_percent::cpu0.data 0.540766 # Average percentage of cache occupancy
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system.cpu0.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy
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system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits
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system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
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system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits
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system.cpu0.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
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system.cpu0.dcache.demand_hits::cpu0.data 180312 # number of demand (read+write) hits
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system.cpu0.dcache.demand_hits::total 180312 # number of demand (read+write) hits
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system.cpu0.dcache.overall_hits::cpu0.data 180312 # number of overall hits
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system.cpu0.dcache.overall_hits::total 180312 # number of overall hits
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system.cpu0.dcache.ReadReq_misses::cpu0.data 324 # number of ReadReq misses
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system.cpu0.dcache.ReadReq_misses::total 324 # number of ReadReq misses
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system.cpu0.dcache.WriteReq_misses::cpu0.data 139 # number of WriteReq misses
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system.cpu0.dcache.WriteReq_misses::total 139 # number of WriteReq misses
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system.cpu0.dcache.demand_misses::cpu0.data 463 # number of demand (read+write) misses
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system.cpu0.dcache.demand_misses::total 463 # number of demand (read+write) misses
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system.cpu0.dcache.overall_misses::cpu0.data 463 # number of overall misses
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system.cpu0.dcache.overall_misses::total 463 # number of overall misses
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system.cpu0.dcache.ReadReq_accesses::cpu0.data 124435 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.WriteReq_accesses::cpu0.data 56340 # number of WriteReq accesses(hits+misses)
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system.cpu0.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
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system.cpu0.dcache.demand_accesses::cpu0.data 180775 # number of demand (read+write) accesses
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system.cpu0.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
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system.cpu0.dcache.overall_accesses::cpu0.data 180775 # number of overall (read+write) accesses
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system.cpu0.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
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system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002604 # miss rate for ReadReq accesses
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system.cpu0.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
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system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.002467 # miss rate for WriteReq accesses
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system.cpu0.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
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system.cpu0.dcache.demand_miss_rate::cpu0.data 0.002561 # miss rate for demand accesses
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system.cpu0.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
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system.cpu0.dcache.overall_miss_rate::cpu0.data 0.002561 # miss rate for overall accesses
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system.cpu0.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
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system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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system.cpu0.dcache.writebacks::writebacks 29 # number of writebacks
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system.cpu0.dcache.writebacks::total 29 # number of writebacks
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system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu1.dtb.fetch_hits 0 # ITB hits
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system.cpu1.dtb.fetch_misses 0 # ITB misses
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system.cpu1.dtb.fetch_acv 0 # ITB acv
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system.cpu1.dtb.fetch_accesses 0 # ITB accesses
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system.cpu1.dtb.read_hits 124435 # DTB read hits
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system.cpu1.dtb.read_misses 8 # DTB read misses
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system.cpu1.dtb.read_acv 0 # DTB read access violations
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system.cpu1.dtb.read_accesses 124443 # DTB read accesses
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system.cpu1.dtb.write_hits 56340 # DTB write hits
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system.cpu1.dtb.write_misses 10 # DTB write misses
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system.cpu1.dtb.write_acv 0 # DTB write access violations
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system.cpu1.dtb.write_accesses 56350 # DTB write accesses
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system.cpu1.dtb.data_hits 180775 # DTB hits
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system.cpu1.dtb.data_misses 18 # DTB misses
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system.cpu1.dtb.data_acv 0 # DTB access violations
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system.cpu1.dtb.data_accesses 180793 # DTB accesses
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system.cpu1.itb.fetch_hits 500019 # ITB hits
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system.cpu1.itb.fetch_misses 13 # ITB misses
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system.cpu1.itb.fetch_acv 0 # ITB acv
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system.cpu1.itb.fetch_accesses 500032 # ITB accesses
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system.cpu1.itb.read_hits 0 # DTB read hits
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system.cpu1.itb.read_misses 0 # DTB read misses
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system.cpu1.itb.read_acv 0 # DTB read access violations
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system.cpu1.itb.read_accesses 0 # DTB read accesses
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system.cpu1.itb.write_hits 0 # DTB write hits
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system.cpu1.itb.write_misses 0 # DTB write misses
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system.cpu1.itb.write_acv 0 # DTB write access violations
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system.cpu1.itb.write_accesses 0 # DTB write accesses
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system.cpu1.itb.data_hits 0 # DTB hits
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system.cpu1.itb.data_misses 0 # DTB misses
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system.cpu1.itb.data_acv 0 # DTB access violations
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system.cpu1.itb.data_accesses 0 # DTB accesses
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system.cpu1.workload.num_syscalls 18 # Number of system calls
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system.cpu1.numCycles 500032 # number of cpu cycles simulated
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system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu1.committedInsts 500001 # Number of instructions committed
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system.cpu1.committedOps 500001 # Number of ops (including micro ops) committed
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system.cpu1.num_int_alu_accesses 474689 # Number of integer alu accesses
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system.cpu1.num_fp_alu_accesses 32 # Number of float alu accesses
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system.cpu1.num_func_calls 14357 # number of times a function call or return occured
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system.cpu1.num_conditional_control_insts 38180 # number of instructions that are conditional controls
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system.cpu1.num_int_insts 474689 # number of integer instructions
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system.cpu1.num_fp_insts 32 # number of float instructions
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system.cpu1.num_int_register_reads 654286 # number of times the integer registers were read
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system.cpu1.num_int_register_writes 371542 # number of times the integer registers were written
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system.cpu1.num_fp_register_reads 32 # number of times the floating registers were read
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system.cpu1.num_fp_register_writes 16 # number of times the floating registers were written
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system.cpu1.num_mem_refs 180793 # number of memory refs
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system.cpu1.num_load_insts 124443 # Number of load instructions
|
|
system.cpu1.num_store_insts 56350 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 0 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 500032 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0 # Percentage of idle cycles
|
|
system.cpu1.icache.tags.replacements 152 # number of replacements
|
|
system.cpu1.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
|
|
system.cpu1.icache.tags.total_refs 499556 # Total number of references to valid blocks.
|
|
system.cpu1.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks.
|
|
system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.tags.occ_blocks::cpu1.inst 218.086151 # Average occupied blocks per requestor
|
|
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.425950 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 499556 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 499556 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 499556 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 499556 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 499556 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 499556 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 463 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 463 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 463 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 463 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 463 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 463 # number of overall misses
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 500019 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 500019 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 500019 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 500019 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.000926 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.000926 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.000926 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dcache.tags.replacements 61 # number of replacements
|
|
system.cpu1.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use
|
|
system.cpu1.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.tags.occ_blocks::cpu1.data 276.872320 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.540766 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 124111 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 56201 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 180312 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 180312 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 180312 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 180312 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 324 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 324 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 139 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 139 # number of WriteReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 463 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 463 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 463 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 463 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 124435 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 56340 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 180775 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 180775 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.002604 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.002467 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.002561 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.002561 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.writebacks::writebacks 29 # number of writebacks
|
|
system.cpu1.dcache.writebacks::total 29 # number of writebacks
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu2.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu2.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu2.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu2.dtb.read_hits 124435 # DTB read hits
|
|
system.cpu2.dtb.read_misses 8 # DTB read misses
|
|
system.cpu2.dtb.read_acv 0 # DTB read access violations
|
|
system.cpu2.dtb.read_accesses 124443 # DTB read accesses
|
|
system.cpu2.dtb.write_hits 56340 # DTB write hits
|
|
system.cpu2.dtb.write_misses 10 # DTB write misses
|
|
system.cpu2.dtb.write_acv 0 # DTB write access violations
|
|
system.cpu2.dtb.write_accesses 56350 # DTB write accesses
|
|
system.cpu2.dtb.data_hits 180775 # DTB hits
|
|
system.cpu2.dtb.data_misses 18 # DTB misses
|
|
system.cpu2.dtb.data_acv 0 # DTB access violations
|
|
system.cpu2.dtb.data_accesses 180793 # DTB accesses
|
|
system.cpu2.itb.fetch_hits 500019 # ITB hits
|
|
system.cpu2.itb.fetch_misses 13 # ITB misses
|
|
system.cpu2.itb.fetch_acv 0 # ITB acv
|
|
system.cpu2.itb.fetch_accesses 500032 # ITB accesses
|
|
system.cpu2.itb.read_hits 0 # DTB read hits
|
|
system.cpu2.itb.read_misses 0 # DTB read misses
|
|
system.cpu2.itb.read_acv 0 # DTB read access violations
|
|
system.cpu2.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu2.itb.write_hits 0 # DTB write hits
|
|
system.cpu2.itb.write_misses 0 # DTB write misses
|
|
system.cpu2.itb.write_acv 0 # DTB write access violations
|
|
system.cpu2.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu2.itb.data_hits 0 # DTB hits
|
|
system.cpu2.itb.data_misses 0 # DTB misses
|
|
system.cpu2.itb.data_acv 0 # DTB access violations
|
|
system.cpu2.itb.data_accesses 0 # DTB accesses
|
|
system.cpu2.workload.num_syscalls 18 # Number of system calls
|
|
system.cpu2.numCycles 500032 # number of cpu cycles simulated
|
|
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu2.committedInsts 500001 # Number of instructions committed
|
|
system.cpu2.committedOps 500001 # Number of ops (including micro ops) committed
|
|
system.cpu2.num_int_alu_accesses 474689 # Number of integer alu accesses
|
|
system.cpu2.num_fp_alu_accesses 32 # Number of float alu accesses
|
|
system.cpu2.num_func_calls 14357 # number of times a function call or return occured
|
|
system.cpu2.num_conditional_control_insts 38180 # number of instructions that are conditional controls
|
|
system.cpu2.num_int_insts 474689 # number of integer instructions
|
|
system.cpu2.num_fp_insts 32 # number of float instructions
|
|
system.cpu2.num_int_register_reads 654286 # number of times the integer registers were read
|
|
system.cpu2.num_int_register_writes 371542 # number of times the integer registers were written
|
|
system.cpu2.num_fp_register_reads 32 # number of times the floating registers were read
|
|
system.cpu2.num_fp_register_writes 16 # number of times the floating registers were written
|
|
system.cpu2.num_mem_refs 180793 # number of memory refs
|
|
system.cpu2.num_load_insts 124443 # Number of load instructions
|
|
system.cpu2.num_store_insts 56350 # Number of store instructions
|
|
system.cpu2.num_idle_cycles 0 # Number of idle cycles
|
|
system.cpu2.num_busy_cycles 500032 # Number of busy cycles
|
|
system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
system.cpu2.idle_fraction 0 # Percentage of idle cycles
|
|
system.cpu2.icache.tags.replacements 152 # number of replacements
|
|
system.cpu2.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
|
|
system.cpu2.icache.tags.total_refs 499556 # Total number of references to valid blocks.
|
|
system.cpu2.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
|
|
system.cpu2.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks.
|
|
system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu2.icache.tags.occ_blocks::cpu2.inst 218.086151 # Average occupied blocks per requestor
|
|
system.cpu2.icache.tags.occ_percent::cpu2.inst 0.425950 # Average percentage of cache occupancy
|
|
system.cpu2.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy
|
|
system.cpu2.icache.ReadReq_hits::cpu2.inst 499556 # number of ReadReq hits
|
|
system.cpu2.icache.ReadReq_hits::total 499556 # number of ReadReq hits
|
|
system.cpu2.icache.demand_hits::cpu2.inst 499556 # number of demand (read+write) hits
|
|
system.cpu2.icache.demand_hits::total 499556 # number of demand (read+write) hits
|
|
system.cpu2.icache.overall_hits::cpu2.inst 499556 # number of overall hits
|
|
system.cpu2.icache.overall_hits::total 499556 # number of overall hits
|
|
system.cpu2.icache.ReadReq_misses::cpu2.inst 463 # number of ReadReq misses
|
|
system.cpu2.icache.ReadReq_misses::total 463 # number of ReadReq misses
|
|
system.cpu2.icache.demand_misses::cpu2.inst 463 # number of demand (read+write) misses
|
|
system.cpu2.icache.demand_misses::total 463 # number of demand (read+write) misses
|
|
system.cpu2.icache.overall_misses::cpu2.inst 463 # number of overall misses
|
|
system.cpu2.icache.overall_misses::total 463 # number of overall misses
|
|
system.cpu2.icache.ReadReq_accesses::cpu2.inst 500019 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.icache.demand_accesses::cpu2.inst 500019 # number of demand (read+write) accesses
|
|
system.cpu2.icache.demand_accesses::total 500019 # number of demand (read+write) accesses
|
|
system.cpu2.icache.overall_accesses::cpu2.inst 500019 # number of overall (read+write) accesses
|
|
system.cpu2.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
|
|
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.000926 # miss rate for ReadReq accesses
|
|
system.cpu2.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
|
|
system.cpu2.icache.demand_miss_rate::cpu2.inst 0.000926 # miss rate for demand accesses
|
|
system.cpu2.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
|
|
system.cpu2.icache.overall_miss_rate::cpu2.inst 0.000926 # miss rate for overall accesses
|
|
system.cpu2.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
|
|
system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu2.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu2.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.dcache.tags.replacements 61 # number of replacements
|
|
system.cpu2.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use
|
|
system.cpu2.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
|
|
system.cpu2.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
|
|
system.cpu2.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks.
|
|
system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu2.dcache.tags.occ_blocks::cpu2.data 276.872320 # Average occupied blocks per requestor
|
|
system.cpu2.dcache.tags.occ_percent::cpu2.data 0.540766 # Average percentage of cache occupancy
|
|
system.cpu2.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy
|
|
system.cpu2.dcache.ReadReq_hits::cpu2.data 124111 # number of ReadReq hits
|
|
system.cpu2.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
|
|
system.cpu2.dcache.WriteReq_hits::cpu2.data 56201 # number of WriteReq hits
|
|
system.cpu2.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
|
|
system.cpu2.dcache.demand_hits::cpu2.data 180312 # number of demand (read+write) hits
|
|
system.cpu2.dcache.demand_hits::total 180312 # number of demand (read+write) hits
|
|
system.cpu2.dcache.overall_hits::cpu2.data 180312 # number of overall hits
|
|
system.cpu2.dcache.overall_hits::total 180312 # number of overall hits
|
|
system.cpu2.dcache.ReadReq_misses::cpu2.data 324 # number of ReadReq misses
|
|
system.cpu2.dcache.ReadReq_misses::total 324 # number of ReadReq misses
|
|
system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses
|
|
system.cpu2.dcache.WriteReq_misses::total 139 # number of WriteReq misses
|
|
system.cpu2.dcache.demand_misses::cpu2.data 463 # number of demand (read+write) misses
|
|
system.cpu2.dcache.demand_misses::total 463 # number of demand (read+write) misses
|
|
system.cpu2.dcache.overall_misses::cpu2.data 463 # number of overall misses
|
|
system.cpu2.dcache.overall_misses::total 463 # number of overall misses
|
|
system.cpu2.dcache.ReadReq_accesses::cpu2.data 124435 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.dcache.WriteReq_accesses::cpu2.data 56340 # number of WriteReq accesses(hits+misses)
|
|
system.cpu2.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
|
|
system.cpu2.dcache.demand_accesses::cpu2.data 180775 # number of demand (read+write) accesses
|
|
system.cpu2.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
|
|
system.cpu2.dcache.overall_accesses::cpu2.data 180775 # number of overall (read+write) accesses
|
|
system.cpu2.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
|
|
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.002604 # miss rate for ReadReq accesses
|
|
system.cpu2.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
|
|
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.002467 # miss rate for WriteReq accesses
|
|
system.cpu2.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
|
|
system.cpu2.dcache.demand_miss_rate::cpu2.data 0.002561 # miss rate for demand accesses
|
|
system.cpu2.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
|
|
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.002561 # miss rate for overall accesses
|
|
system.cpu2.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
|
|
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu2.dcache.writebacks::writebacks 29 # number of writebacks
|
|
system.cpu2.dcache.writebacks::total 29 # number of writebacks
|
|
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu3.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu3.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu3.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu3.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu3.dtb.read_hits 124435 # DTB read hits
|
|
system.cpu3.dtb.read_misses 8 # DTB read misses
|
|
system.cpu3.dtb.read_acv 0 # DTB read access violations
|
|
system.cpu3.dtb.read_accesses 124443 # DTB read accesses
|
|
system.cpu3.dtb.write_hits 56340 # DTB write hits
|
|
system.cpu3.dtb.write_misses 10 # DTB write misses
|
|
system.cpu3.dtb.write_acv 0 # DTB write access violations
|
|
system.cpu3.dtb.write_accesses 56350 # DTB write accesses
|
|
system.cpu3.dtb.data_hits 180775 # DTB hits
|
|
system.cpu3.dtb.data_misses 18 # DTB misses
|
|
system.cpu3.dtb.data_acv 0 # DTB access violations
|
|
system.cpu3.dtb.data_accesses 180793 # DTB accesses
|
|
system.cpu3.itb.fetch_hits 500019 # ITB hits
|
|
system.cpu3.itb.fetch_misses 13 # ITB misses
|
|
system.cpu3.itb.fetch_acv 0 # ITB acv
|
|
system.cpu3.itb.fetch_accesses 500032 # ITB accesses
|
|
system.cpu3.itb.read_hits 0 # DTB read hits
|
|
system.cpu3.itb.read_misses 0 # DTB read misses
|
|
system.cpu3.itb.read_acv 0 # DTB read access violations
|
|
system.cpu3.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu3.itb.write_hits 0 # DTB write hits
|
|
system.cpu3.itb.write_misses 0 # DTB write misses
|
|
system.cpu3.itb.write_acv 0 # DTB write access violations
|
|
system.cpu3.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu3.itb.data_hits 0 # DTB hits
|
|
system.cpu3.itb.data_misses 0 # DTB misses
|
|
system.cpu3.itb.data_acv 0 # DTB access violations
|
|
system.cpu3.itb.data_accesses 0 # DTB accesses
|
|
system.cpu3.workload.num_syscalls 18 # Number of system calls
|
|
system.cpu3.numCycles 500032 # number of cpu cycles simulated
|
|
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu3.committedInsts 500001 # Number of instructions committed
|
|
system.cpu3.committedOps 500001 # Number of ops (including micro ops) committed
|
|
system.cpu3.num_int_alu_accesses 474689 # Number of integer alu accesses
|
|
system.cpu3.num_fp_alu_accesses 32 # Number of float alu accesses
|
|
system.cpu3.num_func_calls 14357 # number of times a function call or return occured
|
|
system.cpu3.num_conditional_control_insts 38180 # number of instructions that are conditional controls
|
|
system.cpu3.num_int_insts 474689 # number of integer instructions
|
|
system.cpu3.num_fp_insts 32 # number of float instructions
|
|
system.cpu3.num_int_register_reads 654286 # number of times the integer registers were read
|
|
system.cpu3.num_int_register_writes 371542 # number of times the integer registers were written
|
|
system.cpu3.num_fp_register_reads 32 # number of times the floating registers were read
|
|
system.cpu3.num_fp_register_writes 16 # number of times the floating registers were written
|
|
system.cpu3.num_mem_refs 180793 # number of memory refs
|
|
system.cpu3.num_load_insts 124443 # Number of load instructions
|
|
system.cpu3.num_store_insts 56350 # Number of store instructions
|
|
system.cpu3.num_idle_cycles 0 # Number of idle cycles
|
|
system.cpu3.num_busy_cycles 500032 # Number of busy cycles
|
|
system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
system.cpu3.idle_fraction 0 # Percentage of idle cycles
|
|
system.cpu3.icache.tags.replacements 152 # number of replacements
|
|
system.cpu3.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
|
|
system.cpu3.icache.tags.total_refs 499556 # Total number of references to valid blocks.
|
|
system.cpu3.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
|
|
system.cpu3.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks.
|
|
system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu3.icache.tags.occ_blocks::cpu3.inst 218.086151 # Average occupied blocks per requestor
|
|
system.cpu3.icache.tags.occ_percent::cpu3.inst 0.425950 # Average percentage of cache occupancy
|
|
system.cpu3.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy
|
|
system.cpu3.icache.ReadReq_hits::cpu3.inst 499556 # number of ReadReq hits
|
|
system.cpu3.icache.ReadReq_hits::total 499556 # number of ReadReq hits
|
|
system.cpu3.icache.demand_hits::cpu3.inst 499556 # number of demand (read+write) hits
|
|
system.cpu3.icache.demand_hits::total 499556 # number of demand (read+write) hits
|
|
system.cpu3.icache.overall_hits::cpu3.inst 499556 # number of overall hits
|
|
system.cpu3.icache.overall_hits::total 499556 # number of overall hits
|
|
system.cpu3.icache.ReadReq_misses::cpu3.inst 463 # number of ReadReq misses
|
|
system.cpu3.icache.ReadReq_misses::total 463 # number of ReadReq misses
|
|
system.cpu3.icache.demand_misses::cpu3.inst 463 # number of demand (read+write) misses
|
|
system.cpu3.icache.demand_misses::total 463 # number of demand (read+write) misses
|
|
system.cpu3.icache.overall_misses::cpu3.inst 463 # number of overall misses
|
|
system.cpu3.icache.overall_misses::total 463 # number of overall misses
|
|
system.cpu3.icache.ReadReq_accesses::cpu3.inst 500019 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.icache.demand_accesses::cpu3.inst 500019 # number of demand (read+write) accesses
|
|
system.cpu3.icache.demand_accesses::total 500019 # number of demand (read+write) accesses
|
|
system.cpu3.icache.overall_accesses::cpu3.inst 500019 # number of overall (read+write) accesses
|
|
system.cpu3.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
|
|
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.000926 # miss rate for ReadReq accesses
|
|
system.cpu3.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
|
|
system.cpu3.icache.demand_miss_rate::cpu3.inst 0.000926 # miss rate for demand accesses
|
|
system.cpu3.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
|
|
system.cpu3.icache.overall_miss_rate::cpu3.inst 0.000926 # miss rate for overall accesses
|
|
system.cpu3.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
|
|
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu3.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu3.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu3.dcache.tags.replacements 61 # number of replacements
|
|
system.cpu3.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use
|
|
system.cpu3.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
|
|
system.cpu3.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
|
|
system.cpu3.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks.
|
|
system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu3.dcache.tags.occ_blocks::cpu3.data 276.872320 # Average occupied blocks per requestor
|
|
system.cpu3.dcache.tags.occ_percent::cpu3.data 0.540766 # Average percentage of cache occupancy
|
|
system.cpu3.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy
|
|
system.cpu3.dcache.ReadReq_hits::cpu3.data 124111 # number of ReadReq hits
|
|
system.cpu3.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
|
|
system.cpu3.dcache.WriteReq_hits::cpu3.data 56201 # number of WriteReq hits
|
|
system.cpu3.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
|
|
system.cpu3.dcache.demand_hits::cpu3.data 180312 # number of demand (read+write) hits
|
|
system.cpu3.dcache.demand_hits::total 180312 # number of demand (read+write) hits
|
|
system.cpu3.dcache.overall_hits::cpu3.data 180312 # number of overall hits
|
|
system.cpu3.dcache.overall_hits::total 180312 # number of overall hits
|
|
system.cpu3.dcache.ReadReq_misses::cpu3.data 324 # number of ReadReq misses
|
|
system.cpu3.dcache.ReadReq_misses::total 324 # number of ReadReq misses
|
|
system.cpu3.dcache.WriteReq_misses::cpu3.data 139 # number of WriteReq misses
|
|
system.cpu3.dcache.WriteReq_misses::total 139 # number of WriteReq misses
|
|
system.cpu3.dcache.demand_misses::cpu3.data 463 # number of demand (read+write) misses
|
|
system.cpu3.dcache.demand_misses::total 463 # number of demand (read+write) misses
|
|
system.cpu3.dcache.overall_misses::cpu3.data 463 # number of overall misses
|
|
system.cpu3.dcache.overall_misses::total 463 # number of overall misses
|
|
system.cpu3.dcache.ReadReq_accesses::cpu3.data 124435 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.dcache.WriteReq_accesses::cpu3.data 56340 # number of WriteReq accesses(hits+misses)
|
|
system.cpu3.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
|
|
system.cpu3.dcache.demand_accesses::cpu3.data 180775 # number of demand (read+write) accesses
|
|
system.cpu3.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
|
|
system.cpu3.dcache.overall_accesses::cpu3.data 180775 # number of overall (read+write) accesses
|
|
system.cpu3.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
|
|
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.002604 # miss rate for ReadReq accesses
|
|
system.cpu3.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
|
|
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.002467 # miss rate for WriteReq accesses
|
|
system.cpu3.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
|
|
system.cpu3.dcache.demand_miss_rate::cpu3.data 0.002561 # miss rate for demand accesses
|
|
system.cpu3.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
|
|
system.cpu3.dcache.overall_miss_rate::cpu3.data 0.002561 # miss rate for overall accesses
|
|
system.cpu3.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
|
|
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu3.dcache.writebacks::writebacks 29 # number of writebacks
|
|
system.cpu3.dcache.writebacks::total 29 # number of writebacks
|
|
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.tags.replacements 0 # number of replacements
|
|
system.l2c.tags.tagsinuse 1962.780232 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 332 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 0.113233 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 17.466765 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 267.152061 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 219.176305 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 267.152061 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 219.176305 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.inst 267.152061 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.data 219.176305 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu3.inst 267.152061 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu3.data 219.176305 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.000267 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.004076 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.003344 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.004076 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.003344 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.inst 0.004076 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.data 0.003344 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu3.inst 0.004076 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu3.data 0.003344 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.029950 # Average percentage of cache occupancy
|
|
system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 60 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.inst 60 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu3.inst 60 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 276 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 116 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 116 # number of Writeback hits
|
|
system.l2c.demand_hits::cpu0.inst 60 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 9 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 60 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.inst 60 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu3.inst 60 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 276 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.inst 60 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 9 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 60 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 9 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.inst 60 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.data 9 # number of overall hits
|
|
system.l2c.overall_hits::cpu3.inst 60 # number of overall hits
|
|
system.l2c.overall_hits::cpu3.data 9 # number of overall hits
|
|
system.l2c.overall_hits::total 276 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.inst 403 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.data 315 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.inst 403 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.data 315 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.inst 403 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.data 315 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu3.inst 403 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu3.data 315 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 139 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 139 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu2.data 139 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu3.data 139 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses
|
|
system.l2c.demand_misses::cpu0.inst 403 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 454 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 403 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 454 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.inst 403 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.data 454 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu3.inst 403 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu3.data 454 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 3428 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.inst 403 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 454 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 403 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 454 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.inst 403 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.data 454 # number of overall misses
|
|
system.l2c.overall_misses::cpu3.inst 403 # number of overall misses
|
|
system.l2c.overall_misses::cpu3.data 454 # number of overall misses
|
|
system.l2c.overall_misses::total 3428 # number of overall misses
|
|
system.l2c.ReadReq_accesses::cpu0.inst 463 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.data 324 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.inst 463 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.data 324 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu2.inst 463 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu2.data 324 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu3.inst 463 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu3.data 324 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::writebacks 116 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 139 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 139 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu2.data 139 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu3.data 139 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.inst 463 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 463 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 463 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 463 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.inst 463 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.data 463 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu3.inst 463 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu3.data 463 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 463 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 463 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 463 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 463 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.inst 463 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.data 463 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu3.inst 463 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu3.data 463 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.inst 0.870410 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.data 0.972222 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.inst 0.870410 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.data 0.972222 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu2.inst 0.870410 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::total 0.912325 # miss rate for ReadReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.870410 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.980562 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.870410 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.980562 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.inst 0.870410 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.data 0.980562 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu3.inst 0.870410 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu3.data 0.980562 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.925486 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.870410 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.980562 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.870410 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.980562 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.inst 0.870410 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.data 0.980562 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu3.inst 0.870410 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu3.data 0.980562 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.925486 # miss rate for overall accesses
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|