Ali Saidi ba14d6d0e1 Bug fixes in the TLB ... Make our replacement algorithm same as legion (although not same as the spec) itb should be 64 entries not 48 src/arch/sparc/tlb.cc: Bug fixes in the TLB Make our replacement algorithm same as legion (although not same as the spec) src/arch/sparc/tlb.hh: Make our replacement algorithm same as legion (although not same as the spec) src/python/m5/objects/SparcTLB.py: itb should be 64 entries too --HG-- extra : convert_revision : 1b5cb3597091e3cfe293e94f6f2219b1e621c35f		2006-12-27 14:38:07 -05:00
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arch	Bug fixes in the TLB	2006-12-27 14:38:07 -05:00
base	cast chars to int when we want to print integers so we get a number	2006-12-18 14:07:52 -08:00
cpu	Compare legion and m5 tlbs for differences	2006-12-27 14:35:23 -05:00
dev	little fixes i noticed while searching for reason for address range issues (but these weren't the cause of the problem).	2006-12-15 17:55:47 -05:00
doxygen	Fix up doxygen.	2006-08-14 19:25:07 -04:00
kern	Moved the Alpha MiscRegFile into it's own file, and got rid of the Alpha specific DepTag constants.	2006-11-09 21:30:48 -05:00
mem	Change MemoryAccess dprintfs to print the data as well	2006-12-27 14:32:26 -05:00
python	Bug fixes in the TLB	2006-12-27 14:38:07 -05:00
sim	Load the hypervisor symbols twice, once with an address mask so that we can get symbols for where it's copied to in memory	2006-11-30 15:51:54 -05:00
unittest	Fix unittest compiles	2006-12-18 14:08:42 -08:00
Doxyfile	Fix up doxygen.	2006-08-14 19:25:07 -04:00
SConscript	Turn cache MissQueue/BlockingBuffer into virtual object	2006-12-04 09:10:53 -08:00