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gem5/ext/mcpat/regression/test-4/power_region0.xml
Yasuko Eckert fbe3688de3 ext: Add a McPAT regression tester 
Add a regression tester to McPAT. Joel Hestness wrote these tests and Yasuko
Eckert modified them to reflect the new McPAT interface and other changes
the previous patch made.
2014-06-04 07:48:20 -07:00

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<?xml version="1.0" ?>
<component id="root" name="root">
<component id="system" name="system" type="System">
<param name="core_tech_node" value="40"/>
<param name="target_core_clockrate" value="2400"/>
<param name="temperature" value="360"/>
<param name="interconnect_projection_type" value="0"/>
<param name="device_type" value="0"/>
<param name="machine_bits" value="64"/>
<param name="virtual_address_width" value="64"/>
<param name="physical_address_width" value="52"/>
<param name="virtual_memory_page_size" value="4096"/>
<param name="wire_is_mat_type" value="2"/>
<param name="wire_os_mat_type" value="2"/>
<param name="delay_wt" value="100"/>
<param name="area_wt" value="0"/>
<param name="dynamic_power_wt" value="100"/>
<param name="leakage_power_wt" value="0"/>
<param name="cycle_time_wt" value="0"/>
<param name="delay_dev" value="10000"/>
<param name="area_dev" value="10000"/>
<param name="dynamic_power_dev" value="10000"/>
<param name="leakage_power_dev" value="10000"/>
<param name="cycle_time_dev" value="10000"/>
<param name="ed" value="2"/>
<param name="burst_len" value="1"/>
<param name="int_prefetch_w" value="1"/>
<param name="page_sz_bits" value="0"/>
<param name="rpters_in_htree" value="1"/>
<param name="ver_htree_wires_over_array" value="0"/>
<param name="nuca" value="0"/>
<param name="nuca_bank_count" value="0"/>
<param name="force_cache_config" value="0"/>
<param name="wt" value="0"/>
<param name="force_wiretype" value="0"/>
<param name="print_detail" value="1"/>
<param name="add_ecc_b_" value="1"/>
<stat name="total_cycles" value="1856694"/>
<component id="system.core0" name="core0" type="Core">
<param name="opt_local" value="0"/>
<param name="clock_rate" value="2000"/>
<param name="instruction_length" value="32"/>
<param name="opcode_width" value="6"/>
<param name="machine_type" value="1"/>
<param name="number_hardware_threads" value="1"/>
<param name="fetch_width" value="1"/>
<param name="number_instruction_fetch_ports" value="1"/>
<param name="decode_width" value="1"/>
<param name="issue_width" value="1"/>
<param name="peak_issue_width" value="1"/>
<param name="commit_width" value="1"/>
<param name="fp_issue_width" value="1"/>
<param name="prediction_width" value="1"/>
<param name="int_pipelines" value="1"/>
<param name="fp_pipelines" value="1"/>
<param name="int_pipeline_depth" value="7"/>
<param name="fp_pipeline_depth" value="10"/>
<param name="ALU_per_core" value="1"/>
<param name="FPU_per_core" value="1"/>
<param name="MUL_per_core" value="1"/>
<param name="instruction_buffer_size" value="16"/>
<param name="instruction_window_scheme" value="0"/>
<param name="instruction_window_size" value="0"/>
<param name="fp_instruction_window_size" value="0"/>
<param name="ROB_size" value="0"/>
<param name="archi_Regs_IRF_size" value="32"/>
<param name="archi_Regs_FRF_size" value="32"/>
<param name="phy_Regs_IRF_size" value="32"/>
<param name="phy_Regs_FRF_size" value="32"/>
<param name="rename_scheme" value="0"/>
<param name="register_window_size" value="0"/>
<param name="store_buffer_size" value="8"/>
<param name="load_buffer_size" value="0"/>
<param name="memory_ports" value="1"/>
<param name="RAS_size" value="32"/>
<param name="execu_wire_mat_type" value="2"/>
<param name="execu_bypass_base_width" value="1"/>
<param name="execu_bypass_base_height" value="1"/>
<param name="execu_bypass_start_wiring_level"value="3"/>
<param name="execu_bypass_route_over_perc" value="1"/>
<param name="globalCheckpoint" value="32"/>
<param name="perThreadState" value="8"/>
<param name="ROB_assoc" value="1"/>
<param name="ROB_nbanks" value="1"/>
<param name="ROB_tag_width" value="0"/>
<param name="scheduler_assoc" value="0"/>
<param name="scheduler_nbanks" value="1"/>
<param name="register_window_assoc" value="1"/>
<param name="register_window_nbanks" value="1"/>
<param name="register_window_tag_width" value="0"/>
<param name="register_window_rw_ports" value="1"/>
<param name="phy_Regs_IRF_assoc" value="1"/>
<param name="phy_Regs_IRF_nbanks" value="1"/>
<param name="phy_Regs_IRF_tag_width" value="0"/>
<param name="phy_Regs_IRF_rd_ports" value="1"/>
<param name="phy_Regs_IRF_wr_ports" value="1"/>
<param name="phy_Regs_FRF_assoc" value="1"/>
<param name="phy_Regs_FRF_nbanks" value="1"/>
<param name="phy_Regs_FRF_tag_width" value="0"/>
<param name="phy_Regs_FRF_rd_ports" value="1"/>
<param name="phy_Regs_FRF_wr_ports" value="1"/>
<param name="front_rat_nbanks" value="1"/>
<param name="front_rat_rw_ports" value="1"/>
<param name="retire_rat_nbanks" value="1"/>
<param name="retire_rat_rw_ports" value="0"/>
<param name="freelist_nbanks" value="1"/>
<param name="freelist_rw_ports" value="1"/>
<param name="load_buffer_assoc" value="0"/>
<param name="load_buffer_nbanks" value="1"/>
<param name="store_buffer_assoc" value="0"/>
<param name="store_buffer_nbanks" value="1"/>
<param name="instruction_buffer_assoc" value="1"/>
<param name="instruction_buffer_nbanks" value="1"/>
<param name="instruction_buffer_tag_width" value="0"/>
<stat name="total_instructions" value="332405"/>
<stat name="int_instructions" value="330557"/>
<stat name="fp_instructions" value="1649"/>
<stat name="branch_instructions" value="32405"/>
<stat name="branch_mispredictions" value="4132"/>
<stat name="load_instructions" value="45636"/>
<stat name="store_instructions" value="44771"/>
<stat name="committed_instructions" value="332405"/>
<stat name="committed_int_instructions" value="330557"/>
<stat name="committed_fp_instructions" value="1649"/>
<stat name="total_cycles" value="9496951709"/>
<stat name="idle_cycles" value="103"/>
<stat name="busy_cycles" value="9496951606"/>
<stat name="ROB_reads" value="332405"/>
<stat name="ROB_writes" value="332405"/>
<stat name="rename_reads" value="960725"/>
<stat name="rename_writes" value="317221"/>
<stat name="fp_rename_reads" value="2772"/>
<stat name="fp_rename_writes" value="1288"/>
<stat name="inst_window_reads" value="330557"/>
<stat name="inst_window_writes" value="330557"/>
<stat name="inst_window_wakeup_accesses" value="330557"/>
<stat name="fp_inst_window_reads" value="1649"/>
<stat name="fp_inst_window_writes" value="1649"/>
<stat name="fp_inst_window_wakeup_accesses" value="1649"/>
<stat name="int_regfile_reads" value="960725"/>
<stat name="float_regfile_reads" value="2772"/>
<stat name="int_regfile_writes" value="317221"/>
<stat name="float_regfile_writes" value="1288"/>
<stat name="function_calls" value="2546"/>
<stat name="context_switches" value="3"/>
<stat name="ialu_accesses" value="330157"/>
<stat name="fpu_accesses" value="1649"/>
<stat name="mul_accesses" value="400"/>
<stat name="cdb_alu_accesses" value="330157"/>
<stat name="cdb_mul_accesses" value="400"/>
<stat name="cdb_fpu_accesses" value="1649"/>
<stat name="IFU_duty_cycle" value="1"/>
<stat name="LSU_duty_cycle" value="1"/>
<stat name="MemManU_I_duty_cycle" value="1"/>
<stat name="MemManU_D_duty_cycle" value="1"/>
<stat name="ALU_duty_cycle" value="1"/>
<stat name="MUL_duty_cycle" value="1"/>
<stat name="FPU_duty_cycle" value="1"/>
<stat name="ALU_cdb_duty_cycle" value="1"/>
<stat name="MUL_cdb_duty_cycle" value="1"/>
<stat name="FPU_cdb_duty_cycle" value="1"/>
<component id="system.core0.bpred" name="bpred" type="BranchPredictor">
<param name="assoc" value="1"/>
<param name="nbanks" value="1"/>
<param name="local_l1_predictor_size" value="10"/>
<param name="local_l2_predictor_size" value="3"/>
<param name="local_predictor_entries" value="1024"/>
<param name="global_predictor_entries" value="4096"/>
<param name="global_predictor_bits" value="2"/>
<param name="chooser_predictor_entries" value="4096"/>
<param name="chooser_predictor_bits" value="2"/>
</component>
<component id="system.core0.itlb" name="itlb" type="InstructionTLB">
<param name="number_entries" value="64"/>
<param name="latency" value="2"/>
<param name="throughput" value="2"/>
<param name="assoc" value="0"/>
<param name="nbanks" value="1"/>
<stat name="total_accesses" value="72"/>
<stat name="total_misses" value="36"/>
<stat name="conflicts" value="0"/>
</component>
<component id="system.core0.dtlb" name="dtlb" type="DataTLB">
<param name="number_entries" value="64"/>
<param name="latency" value="2"/>
<param name="throughput" value="2"/>
<param name="assoc" value="0"/>
<param name="nbanks" value="1"/>
<stat name="read_accesses" value="534"/>
<stat name="write_accesses" value="0"/>
<stat name="read_misses" value="25"/>
<stat name="write_misses" value="0"/>
<stat name="conflicts" value="0"/>
</component>
<component id="system.core0.btargetbuf" name="btargetbuf" type="BranchTargetBuffer">
<param name="size" value="8192"/>
<param name="block_size" value="4"/>
<param name="assoc" value="2"/>
<param name="num_banks" value="1"/>
<param name="latency" value="1"/>
<param name="throughput" value="3"/>
<param name="rw_ports" value="1"/>
<stat name="read_accesses" value="43"/>
<stat name="write_accesses" value="943"/>
</component>
</component>
</component>
</component>
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