gem5/ext
Alec Roelke e76bfc8764 arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.

Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).

[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
[Fix some minor formatting mistakes.]
Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power <jason@lowepower.com>
2016-11-30 17:10:28 -05:00
..
dnet ext: clang fix for flexible array members 2014-08-13 06:57:19 -04:00
drampower ext: Update DRAMPower 2016-07-01 10:31:36 -05:00
dramsim2 scons: Enable -Wextra by default 2016-01-11 05:52:20 -05:00
dsent ext: dsent: adds a Python interface, drops C++ one 2014-10-11 16:16:00 -05:00
fputils ext: Update fputils to rev 13589cd 2016-11-18 18:08:20 +00:00
iostream3 ext: Replace gzstream with iostream3 from zlib to avoid LGPL 2016-01-11 05:52:18 -05:00
libelf arch: [Patch 1/5] Added RISC-V base instruction set RV64I 2016-11-30 17:10:28 -05:00
libfdt ext lib: add libfdt to enable flattened device tree support 2013-02-15 18:48:59 -05:00
mcpat ext: Add a McPAT regression tester 2014-06-04 07:48:20 -07:00
nomali ext: Update NoMali to external rev f08e0a5 2016-01-29 12:14:21 +00:00
ply ext: disable PLY debugging 2014-03-19 19:18:43 -05:00
sst ext: update SST test config 2016-09-20 15:51:24 +01:00
x11keysym Ext: Add X11 keysym header files to ext directory. 2011-02-09 22:27:37 -06:00